93L24 Datasheet, PDF (3/4 Pages) National Semiconductor (TI) – 5-Bit Comparator

Switching Characteristics
V_CC e a5 0V T_A e a25 C (See Section 1 for test waveforms and output load)
Symbol
Parameter
C_L e 15 pF
Min
Max
t_PLH
Propagation Delay
32
t_PHL
E to AeB E to A^kB A^lB
35
t_PLH
Propagation Delay
54
t_PHL
An to A^lB Bn to A^lB
75
t_PLH
Propagation Delay
70
t_PHL
An to A^kB Bn to A^kB
77
t_PLH
Propagation Delay
100
t_PHL
An or Bn to AeB
102
Units
ns
ns
ns
ns
Functional Description
The 93L24 5-bit comparators use combinational circuitry to
directly generate ‘‘A greater than B’’ and ‘‘A less than B’’
outputs As evident from the logic diagram these ouptuts
are generated in only three gate delays The ‘‘A equals B’’
output is generated in one additional gate delay by decoding
the ‘‘A neither less than nor greater than B’’ condition with a
NOR gate All three outputs are activated by the active LOW
Enable Input (E)
Tying the A^lB output from one device into an A input on
another device and the A^k B output into the corresponding
B input permits easy expansion
The A4 and B4 inputs are the most significant inputs and
A0 B0 the least significant Thus if A4 is HIGH and B4 is
LOW the A^lB output will be HIGH regardless of all other
inputs except E
Logic Diagram
TL F 10199 – 3
3