93L08 Datasheet, PDF (3/4 Pages) National Semiconductor (TI) – Dual 4-Bit Latch

Switching Characteristics
V_CC e a5 0V T_A e a25 C (See Section 3 for waveforms and load configurations)
Symbol
Parameter
C_L e 15 pF
Min
Max
t_PLH
Propagation Delay
45
t_PHL
En to Qn
38
t_PLH
Propagation Delay
27
t_PHL
Dn to Qn
29
t_PHL
Propagation Delay
30
MR to Qn
Functional Description
Data can be entered into the latch when both of the enable
inputs are LOW As long as this logic condition exists the
output of the latch will follow the input If either of the enable
inputs goes HIGH the data present in the latch at that time
is held in the latch and is no longer affected by data input
The master reset overrides all other input conditions and
forces the outputs of all the latches LOW when a LOW sig-
nal is applied to the Master Reset input
Truth Table
MR E0 E1 D
H
L
L
L
H
L
L
H
H
L
H
X
H
H
L
X
H
H
H
X
L
X
X
X
Q_nb₁ e Previous Output State
Q_n e Present Output State
H e HIGH Voltage Level
L e LOW Voltage Level
X e Immaterial
Qn
L
L
Qnb1
Qnb1
Qnb1
L
Units
ns
ns
ns
Operation
Data Entry
Data Entry
Hold
Hold
Hold
Reset
Logic Diagram
TL F 9594 – 3
3