9334 Datasheet, PDF (3/6 Pages) National Semiconductor (TI) – 8-Bit Addressable Latch

Switching Characteristics at V_CC e 5V and T_A e 25 C (See Section 1 for Test Waveforms and Output Load)
Symbol
Parameter
From (Input)
To (Output)
R_L e 400X C_L e 15 pF
Min
Max
Units
t_PLH
Propagation Delay Time
Enable to
Low to High Level Output
Output Fig 1
28
ns
t_PHL
Propagation Delay Time
Enable to
High to Low Level Output
Output Fig 1
27
ns
t_PLH
Propagation Delay Time
Data to
Low to High Level Output
Output Fig 2
35
ns
t_PHL
Propagation Delay Time
Data to
High to Low Level Output
Output Fig 2
28
ns
t_PLH
Propagation Delay Time
Address to
Low to High Level Output
Output Fig 3
35
ns
t_PHL
Propagation Delay Time
Address to
High to Low Level Output
Output Fig 3
35
ns
t_PHL
Propagation Delay Time
Clear to
High to Low Level Output
Output Fig 5
31
ns
Function Tables
E
C
Mode
L
H
Addressable Latch
H
H
Memory
L
L
Active High Eight
Channel Demultiplexer
H
L
Clear
Inputs
Present Output States
Mode
C E D A0 A1 A2 Q0
Q1
Q2
Q3 Q4 Q5 Q6 Q7
LHX X X X
L
L
L
L
L
L
L
L Clear
LLL L L L
L
L
L
L
L
L
L
L
LLH L L L
H
L
L
L
L
L
L
L
LLL H L L
L
L
L
L
L
L
L
L
LLH H L L
L
H
L
L
L
L
L
L



Demultiplex






LLH H H H
L
L
L
L
L
L
L
H
HHX X X
HLL L L
HLH L L
HLL H L
HLH H L






HLL H H
HLH H H
X e Don’t Care Condition
L e Low Voltage Level
H e High Voltage Level
Q_Nb₁ e Previous Output State
X Q_Nb₁
L
L
Q_Nb₁ Q_Nb₁ Q_Nb₁
L
H
Q_Nb₁ Q_Nb₁
L
Q_Nb₁
L
Q_Nb₁
L
Q_Nb₁
H
Q_Nb₁



H Q_Nb₁
H Q_Nb₁
Memory
Addressable
Latch
Q_Nb₁
L
Q_Nb₁ H
3