74LS194A Datasheet, PDF (3/8 Pages) National Semiconductor (TI) – 4-Bit Bidirectional Universal Shift Register

Switching Characteristics at V_CC e 5V and T_A e 25 C (See Section 1 for Test Waveforms and Output Load)
Symbol
Parameter
From (Input)
To (Output)
54LS
C_L e 15 pF
Min
Max
DM74LS
C_L e 50 pF
R_L e 2 kX
Min
Max
Units
f_MAX
Maximum Clock
Frequency
30
20
MHz
t_PLH
Propagation Delay Time
Clock to
Low to High Level Output
Any Q
21
26
ns
t_PHL
Propagation Delay Time
Clock to
High to Low Level Output
Any Q
24
35
ns
t_PHL
Propagation Delay Time
Clear to
High to Low Output
Any Q
26
38
ns
Note 1 All typicals are at V_CC e 5V T_A e 25 C
Note 2 Not more than one output should be shorted at a time and the duration should not exceed one second
Note 3 With all outputs open inputs A through D grounded and 4 5V applied to S0 S1 CLEAR and the serial inputs I_CC is tested with momentary ground then
4 5V applied to CLOCK
Logic Diagram
LS194A
Function Table
TL F 6407 – 2
Inputs
Outputs
Clear
Mode
Clock
Serial
Parallel
Q_A Q_B Q_C Q_D
S1 S0
Left Right A B C D
L
XX
X
X
X
XXXX L
L
L
L
H
XX
L
X
X
X X X X Q_A0 Q_B0 Q_C0 Q_D0
H HH u
X
X
abcd a
b
c
d
H
LH
u
X
H
XXXX
H
Q_An Q_Bn Q_Cn
H
LH
u
X
L
XXXX
L
Q_An Q_Bn Q_Cn
H HL u
H
X
X X X X Q_Bn Q_Cn Q_Dn H
H HL u
L
X
X X X X Q_Bn Q_Cn Q_Dn
L
H
LL
X
X
X
X X X X Q_A0 Q_B0 Q_C0 Q_D0
H e High Level (steady state) L e Low Level (steady state) X e Don’t Care (any input including transitions)
u e Transition from low to high level
a b c d e The level of steady state input at inputs A B C or D respectively
Q_A0 Q_B0 Q_C0 Q_D0 e The level of Q_A Q_B Q_C or Q_D respectively before the indicated steady state input conditions were established
u QAn QBn QCn QDn e The level of QA QB QC respectively before the most-recent transition of the clock
3