54F827SDM Datasheet, PDF (3/8 Pages) National Semiconductor (TI) – 10-Bit Buffers/Line Drivers

Unit Loading Fan Out
54F 74F
Pin Names
Description
UL
HIGH LOW
Input I_IH I_IL
Output I_OH I_OL
OE₁ OE₂
D₀ – D₇
O₀ – O₇
Output Enable Input
10 10
20 mA b0 6 mA
Data Inputs
10 10
20 mA b0 6 mA
Data Outputs TRI-STATE 600 106 6 (80) b12 mA 64 mA (48 mA)
Functional Description
The ’F827 and ’F828 are line drivers designed to be em-
ployed as memory address drivers clock drivers and bus-
oriented transmitters receivers which provide improved PC
board density The devices have TRI-STATE outputs con-
trolled by the Output Enable (OE) pins The outputs can sink
64 mA (48 mA mil) and source 15 mA Input clamp diodes
limit high-speed termination effects
Function Table
Inputs
Outputs
OE
D_n
O_n
’F827
’F828
L
H
H
L
L
L
L
H
H
X
Z
Z
H e HIGH Voltage level
L e LOW Voltage Level
Z e High Impedance
X e Immaterial
Logic Diagrams
’F827
Function
Transparent
Transparent
High Z
TL F 9598 – 4
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays
’F828
TL F 9598 – 11
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays
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