54F823SDM Datasheet, PDF (3/8 Pages) National Semiconductor (TI) – 9-Bit D-Type Flip-Flop

Functional Description
The ’F823 device consists of nine D-type edge-triggered
flip-flops It has TRI-STATE true outputs and is organized in
broadside pinning The buffered Clock (CP) and buffered
Output Enable (OE) are common to all flip-flops The flip-
flops will store the state of their individual D inputs that meet
the setup and hold times requirements on the LOW-to-HIGH
CP transition With the OE LOW the contents of the flip-
flops are available at the outputs When the OE is HIGH the
outputs go to the high impedance state Operation of the
OE input does not affect the state of the flip-flops In addi-
tion to the Clock and Output Enable pins the ’F823 has
Clear (CLR) and Clock Enable (EN) pins
When the CLR is LOW and the OE is LOW the outputs are
LOW When CLR is HIGH data can be entered into the flip-
flops When EN is LOW data on the inputs is transferred to
the outputs on the LOW to HIGH clock transition When the
EN is HIGH the outputs do not change state regardless of
the data or clock inputs transitions This device is ideal for
parity bus interfacing in high performance systems
Inputs
OE CLR EN CP
H
H
L
H
H
H
L
L
H
H
H
X
L
H
H
X
H
L
X
X
L
L
X
X
H
H
LL
H
H
LL
L
H
LL
L
H
LL
L
H
L
H
L
H
L
L
L e LOW Voltage Level
H e HIGH Voltage Level
X e Immaterial
Z e High Impedance
L e LOW-to-HIGH Transition
NC e No Change
Function Table
Internal Output
D
Q
O
X
NC
Z
X
NC
Z
X
NC
Z
X
NC
NC
X
H
Z
X
H
L
H
H
Z
H
L
Z
L
H
L
H
L
H
X
NC
NC
X
NC
NC
Function
Hold
Hold
Hold
Hold
Clear
Clear
Load
Load
Data Available
Data Available
No Change in Data
No Change in Data
Logic Diagram
TL F 9596 – 5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays
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