54ACT818 Datasheet, PDF (3/10 Pages) National Semiconductor (TI) – 8-Bit Diagnostic Register

Block Diagram
Functional Description
Data transfers into the diagnostic register occur on the
LOW-to-HIGH transition of DCLK. Mode and SDI determine
what data source will be loaded. The pipeline register is
loaded on the LOW-to-HIGH transition of PCLK. Mode se-
lects whether the data source is the data input or the diag-
Function Table
DS100251-5
nostic register output. Because of the independence of the
clock inputs, data can be shifted in the diagnostic register via
DCLK and loaded into the pipeline register from the data in-
put via PCLK simultaneously, as long as no setup or hold
times are violated. This simultaneous operation is legal.
Inputs
SDI MODE DCLK PCLK SDO
X
L
N
X
S7
X
L
X
N
S7
L
H
N
X
L
X
H
X
N
SDI
H
H
N
X
H
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
N = LOW-to-HIGH Clock Transition
Outputs
Diagnostic Reg.
SI<SI − 1,
SO<SD_I
NA
SI<YI
Pipeline Reg.
NA
PI<DI
NA
NA
PI<SI
Hold
NA
Operation
Serial Shift; D₇–D₀ Disabled
Normal Load Pipeline Register
Load Diagnostic Register from Y;
DI Disabled
Load Pipeline Register from
Diagnostic Register
Hold Diagnostic Register; DI
Enabled
3
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