LP5552_08 Datasheet, PDF (28/36 Pages) National Semiconductor (TI) – PWI 2.0 and PowerWise Technology Compliant Energy Management Unit

LP5552 Operation
GENERAL DESCRIPTION
The LP5552 is a PowerWise Interface (PWI) 2.0 compliant
energy management unit (EMU) for application or baseband
processors in mobile phones and other portable equipment.
It operates cooperatively with processors using National
Semiconductor’s Advanced Power Controller (APC) to pro-
vide Adaptive Voltage Scaling (AVS) which drastically im-
proves efficiencies compared to conventional power delivery
methods. The LP5552 consists of two high-efficiency switch-
ing DC/DC buck converters to supply two voltage scaling
domains, and five LDOs for supplying additional support cir-
cuitry.
VOLTAGE SCALING
The LP5552 is designed to be used in a voltage scaling sys-
tem to lower the power dissipation of the system. By scaling
supply voltage with the clock frequency of a processor, dra-
matic power savings can be achieved. Two types of voltage
scaling are supported, dynamic voltage scaling (DVS) and
adaptive voltage scaling (AVS). Both Switcher 1 and Switcher
2 support AVS and DVS modes. DVS systems switch be-
tween pre-characterized voltages, which are paired to clock
frequencies used for frequency scaling in the processor. AVS
systems track the processor performance and optimize the
supply voltage to the required performance. AVS is a closed
loop system that provides process and temperature compen-
sation such that for any given processor, temperature, or
clock frequency, the minimum supply voltage is delivered.
POWERWISE INTERFACE
What follows is only a brief description of the parts of the PWI
2.0 spec that are relevant to the LP5552. Please see the PWI
2.0 spec for a complete description.
To support DVS and AVS, the LP5552 is programmable via
the low-power, 2-wire PowerWise Interface (PWI). This serial
interface controls the various voltages and states of all the
regulators in the LP5552.
Both slaves in the LP5552 support the full PWI command set,
other than the optional Extended Register Read and Write, as
described in the PWI 2.0 specification:
• Core Voltage Adjust
• Reset
• Sleep
• Shutdown
• Wakeup
• Register Read
• Register Write
• Authenticate
The 2-wire PWI interface is composed of the SCLK and SPWI
pins on the LP5552. SCLK is always an input to the LP5552
and should be driven by a PowerWise master in the system.
The SCLK clock rate can operate from 32kHz – 15MHz. SPWI
is the bi-directional serial data line. It can drive a 50pF line
and meet timing standards for a 15MHz PWI bus. Both signals
are referenced to the voltage present at V_O2, the LDO2 output
voltage. Both signals contain an internal pull-down resistor of
~1MΩ, in accordance with the PWI 2.0 specification.
SLAVE ADDRESSING DESCRIPTION
PWI 2.0 supports up to 16 logical slaves in the same system.
Four slave address bits are included at the start of every PWI
communications frame to identify which slave is being target-
ed by the PWI master. The LP5552 contains 2 logical slaves
in its package. The 3 MSBs of the LP5552’s slave address
are set by the SA1, SA2, and SA3 pins. They are actively
decoded by the LP5552 on every transaction. The LSB of the
slave address is hard-wired inside the LP5552. Slave ‘N’ will
always be located at SA[0] = 0, and slave ‘N+1’ will always
exist at SA[0] = 1. As an example, if we were to tie SA1 = SA3
= VDD and SA2 = GND in our system, then the LP5552’s
slave ‘N’ would be located at SA[3:0] = 0xA and slave ‘N+1’
would be SA[3:0] = 0xB.
CONTROL AND STATUS SIGNALS
The LP5552 implements all 3 of the PWI 2.0 control and status
signals. ENABLE and RESETN are inputs to the LP5552 that
allow for power-up and power-down sequencing, as well as
resetting the EMU to a known state. Both ENABLE and RE-
SETN must be a logic ‘1’ during normal operation. PWROK is
an indicator to the system that the LP5552 is in regulation and
power is stable. Its output is dependent upon the state of the
two slave devices. See Table 1, “PWROK Value Per Slave
State,” below for details. All 3 signals are asynchronous sig-
nals.
TABLE 1. PWROK Value Per Slave State
STARTUP
ACTIVE
SLEEP
SHUTDOWN
STARTUP
0
1
1
0
ACTIVE
1
1
1
1
SLAVE (N+1)
SLEEP
1
1
1
1
SHUTDOWN
0
1
1
0
General Purpose Outputs
The LP5552 contains 3 digital output pins that can be used
as the system designer sees fit. By default, they are config-
ured as open-drain outputs, outputting a logic ‘0’. They can
be changed to a push-pull CMOS output by clearing Slave ‘N’,
R13[3]. In the open-drain configuration, they can be refer-
enced to any voltage less than the VDD of the LP5552. The
push-pull output mode will reference the high-side to the volt-
age of LDO2.
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