ADC08D500_09 Datasheet, PDF (28/40 Pages) National Semiconductor (TI) – High Performance, Low Power, Dual 8-Bit, 500 MSPS A/D Converter

1.4 REGISTER DESCRIPTION
Eight write-only registers provide several control and config-
uration options in the Extended Control Mode. These regis-
ters have no effect when the device is in the Normal Control
Mode. Each register description below also shows the Power-
On Reset (POR) state of each control bit.
Configuration Register
Addr: 1h (0001b)
W only (0xB2FF)
D15 D14 D13 D12 D11 D10 D9 D8
1 0 1 DCS DCP nDE OV OE
D7 D6 D5 D4 D3 D2 D1 D0
11111111
IMPORTANT: The Configuration Register should not be
written if the DES Enable bit = 1. The DES Enable bit
should first be changed to 0, then the Configuration
Register can be written. Failure to follow this procedure
can cause the internal DES clock generation circuitry to
stop.
Bit 15
Must be set to 1b
Bit 14
Must be set to 0b
Bit 13
Must be set to 1b
Bit 12
DCS: Duty Cycle Stabilizer. When this bit is set
to 1b, a duty cycle stabilization circuit is
applied to the clock input. When this bit is set
to 0b the stabilization circuit is disabled.
Bit 11
DCP: DDR Clock Phase. This bit only has an
effect in the DDR mode. When this bit is set to
0b, the DCLK edges are time-aligned with the
data bus edges ("0° Phase"). When this bit is
set to 1b, the DCLK edges are placed in the
middle of the data bit-cells ("90° Phase"),
using the one-half speed DCLK shown in
Figure 4 as the phase reference.
POR State: 0b
Bit 10
nDE: DDR Enable. When this bit is set to 0b,
data bus clocking follows the DDR (Dual Data
Rate) mode whereby a data word is output
with each rising and falling edge of DCLK.
When this bit is set to a 1b, data bus clocking
follows the SDR (single data rate) mode
whereby each data word is output with either
the rising or falling edge of DCLK, as
determined by the OutEdge bit.
POR State: 0b
Bit 9
OV: Output Voltage. This bit determines the
LVDS outputs' voltage amplitude and has the
same function as the OutV pin that is used in
the normal control mode. When this bit is set
to 1b, the standard output amplitude of 710
mV_P-P is used. When this bit is set to 0b, the
reduced output amplitude of 510 mV_P-P is
used.
POR State: 1b
Bit 8
Bits 7:0
OE: Output Edge. This bit selects the DCLK
edge with which the data words transition in
the SDR mode and has the same effect as the
OutEdge pin in the normal control mode.
When this bit is 1b, the data outputs change
with the rising edge of DCLK+. When this bit is
0b, the data output change with the falling
edge of DCLK+.
POR State: 0b
Must be set to 1b.
I-Channel Offset
Addr: 2h (0010b)
W only (0x007F)
D15 D14 D13 D12 D11 D10 D9 D8
(MSB)
Offset Value
(LSB)
D7 D6 D5 D4 D3 D2 D1 D0
Sign 1 1 1 1 1 1 1
Bits 15:8
Bit 7
Bit 6:0
Offset Value. The input offset of the I-Channel
ADC is adjusted linearly and monotonically by
the value in this field. 00h provides a nominal
zero offset, while FFh provides a nominal 45
mV of offset. Thus, each code step provides
0.176 mV of offset.
POR State: 0000 0000b
Sign bit. 0b gives positive offset, 1b gives
negative offset.
POR State: 0b
Must be set to 1b
I-Channel Full-Scale Voltage Adjust
Addr: 3h (0011b)
W only (0x807F)
D15 D14 D13 D12 D11 D10 D9 D8
(MSB
Adjust Value
)
D7 D6 D5 D4 D3 D2 D1 D0
(LSB 1 1 1 1 1 1 1
)
Bit 15:7
Bits 6:0
Full Scale Voltage Adjust Value. The input full-
scale voltage of the I-Channel ADC is adjusted
linearly and monotonically from the nominal
700 mV_P-P differential by the value in this field.
0000 0000 0
560mV_P-P
1000 0000 0
700mV_P-P
1111 1111 1
840mV_P-P
For best performance, it is recommended that
the value in this field be limited to the range of
0110 0000 0b to 1110 0000 0b. i.e., limit the
amount of adjustment to ±15%. The remaining
±5% headroom allows for the ADC's own full
scale variation .A gain adjustment does not
require ADC re-calibration.
POR State: 1000 0000 0b (no adjustment)
Must be set to 1b
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