ADC08D1000_08 Datasheet, PDF (27/40 Pages) National Semiconductor (TI) – High Performance, Low Power, Dual 8-Bit, 1 GSPS A/D Converter

TABLE 2. Features and modes
Feature
Normal Control Mode
Extended Control Mode
SDR or DDR Clocking
DDR Clocking selected with pin 4
floating. SDR clocking selected when pin
Selected with nDE in the Configuration
Register (1h; bit-10). When the device is
4 not floating.
in DDR mode, address 1h, bit-8 must be
set to 0b.
DDR Clock Phase
Not Selectable (0° Phase Only)
Selected with DCP bit in the
Configuration Register (1h; bit-11).
SDR Data transitions with rising or ^{SDR Data transitions with rising edge of} Selected with OE in the Configuration
falling DCLK edge
DCLK+ when pin 4 is high and on falling
edge when low.
Register (1h; bit-8).
LVDS output level
Normal differential data and DCLK
amplitude selected when pin 3 is high
and reduced amplitude selected when
low.
Selected with the OV in the
Configuration Register (1h; bit-9).
Power-On Calibration Delay
Short delay selected when pin 127 is low
and longer delay selected when high ^{Short delay only.}
Full-Scale Range
Options (650 mV_P-P or 870 mV_P-P)
selected with pin 14. Selected range
applies to both channels.
Up to 512 step adjustments over a
nominal range specified in ??1.4.
Selected using the Input Full-Scale
Adjust register (3h; bits-7 thru 15).
Input Offset Adjust
Not possible
512 steps of adjustment using the Input
Offset register (2h; bits-7 thru 15) as
specified in ??1.4
Dual Edge Sampling Selection Enabled with pin 127
Enabled through DES Enable Register.
Dual Edge Sampling Input
Channel Selection
Only I-Channel Input can be used
Either I- or Q-Channel input may be
sampled by both ADCs.
DES Sampling Clock Adjustment
The Clock Phase is adjusted
automatically
Automatic Clock Phase control can be
selected by setting bit 14 in the DES
Enable register (Dh). The clock phase
can also be adjusted manually through
the Coarse & Fine registers (Eh and Fh).
The default state of the Extended Control Mode is set upon
power-on reset (internally performed by the device) and is
shown in Table 3.
TABLE 3. Extended Control Mode Operation
(Pin 14 Floating)
Feature
Extended Control Mode
Default State
SDR or DDR Clocking
DDR Clocking
DDR Clock Phase
Data changes with DCLK
edge (0° phase)
LVDS Output Amplitude
Calibration Delay
Normal amplitude
(710 mV_P-P)
Short Delay
Full-Scale Range
700 mV nominal for both
channels
Input Offset Adjust
No adjustment for either
channel
Dual Edge Sampling (DES)
Not enabled
1.3 THE SERIAL INTERFACE
The 3-pin serial interface is enabled only when the device is
in the Extended Control mode. The pins of this interface are
Serial Clock (SCLK), Serial Data (SDATA) and Serial Inter-
face Chip Select (SCS) Eight write only registers are acces-
sible through this serial interface.
SCS: This signal should be asserted low while accessing a
register through the serial interface. Setup and hold times with
respect to the SCLK must be observed.
SCLK: Serial data input is accepted with the rising edge of
this signal. There is no minimum frequency requirement for
SCLK.
SDATA: Each register access requires a specific 32-bit pat-
tern at this input. This pattern consists of a header, register
address and register value. The data is shifted in MSB first.
Setup and hold times with respect to the SCLK must be ob-
served. See the Timing Diagram.
Each Register access consists of 32 bits, as shown in Figure
5 of the Timing Diagrams. The fixed header pattern is 0000
0000 0001 (eleven zeros followed by a 1). The loading se-
quence is such that a "0" is loaded first. These 12 bits form
the header. The next 4 bits are the address of the register that
is to be written to and the last 16 bits are the data written to
the addressed register. The addresses of the various regis-
ters are indicated in Table 4.
Refer to the Register Description (Section 1.4) for information
on the data to be written to the registers.
Subsequent register accesses may be performed immediate-
ly, starting with the 33rd SCLK. This means that the SCS input
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