LM49370 Datasheet, PDF (26/100 Pages) National Semiconductor (TI) – Audio Sub-System with an Ultra Low EMI, Spread Spectrum, Class D Loudspeaker Amplifier

12.8 PLL N MODULUS CONFIGURATION REGISTER
This register is used to control the modulation applied to the feedback divider of the PLL. (Note 15)
TABLE 9. PLL_N_MOD (0x05h)
Bits
Field
Description
4:0
PLL_N_MOD This programs the PLL N divider's fractional component:
PLL_N_MOD
0
1
2 to 30
31
6:5 PLL_CLK_SEL This selects the clock to be used as input for the audio PLL.
PLL_INPUT_CLK
00₂
01₂
10₂
11₂
7
RSVD
Reserved.
Fractional Addition
0/32
1/32
2/32 to 30/32
31/32
MCLK
I2S_CLK_IN
PCM_CLK_IN
—
The complete N divider is a fractional divider as such:
N = PLL_N + PLL_N_MOD/32
If the modulus input is zero then the N divider is simply an integer N divider. The output from the PLL is determined by the following
formula:
F_out = (F_in*N)/(M*P)
Note 15: See Further Notes on PLL Programming for more details.
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