LM4935 Datasheet, PDF (26/112 Pages) National Semiconductor (TI) – Audio Sub-System with Dual-Mode Stereo Headphone and Mono High Efficiency Loudspeaker Amplifiers and Multi-Purpose ADC

12.0 Status & Control Registers (Continued)
12.6 PLL N DIVIDER CONFIGURATION REGISTER
This register is used to control the feedback divider of the PLL.
TABLE 7. PLL_N (0x03h)
Bits
Field
Description
7:0
PLL_N
Programs the PLL feedback divider as follows:
PLL_N
0 to 10
11
12
13
14
…
249
250 to 255
Feedback Divider Value
10
11
12
13
14
…
249
250
The N divider should be set such that the output of the divider is between 0.5 MHz and 5 MHz. (Fin/M)*N will be the target resting
VCO frequency, F_VCO. The N divider should be set such that 40 MHz < (Fin/M)*N < 60 MHz. Fin/M is often referred to as F_comp
(comparison frequency) or F_ref (reference frequency), in this document F_comp is used.
The integer division of the N divider is derived from PLL_N such that:
For 9 < PLL_N < 251: N = PLL_N
Note 12: See Further Notes on PLL Programming for further details.
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