TP3420A Datasheet, PDF (25/32 Pages) National Semiconductor (TI) – ISDN S/T Interface Device

Timing Characteristics
Symbol
Parameter
Conditions
MCLK SYSTEM CLOCK (See Figure 5)
F_MCK
Master Clock Frequency
Master Clock Tolerance
MCLK/XTAL Input Clock Jitter
External Clock Source
t_MH,
Clock Pulse Width
V_IH = V_CC − 0.5V
t_ML
Hi & Low for MCLK
V_IL = 0.5V
t_MR,
Rise and Fall Time
Used as a
t_MF
of MCLK
Logic Input
MICROWIRE CONTROL INTERFACE (See Figure 5)
t_CH
CCLK High Duration
t_CL
CCLK Low Duration
t_SIC
Setup Time, CI
Valid to CCLK Edge
t_HCI
Hold Time, CCLK
High to CI Invalid
t_DCSO
Delay Time from CS
Low to CO Valid
Bit C7 only
t_DCO
Delay Time from CCLK Edge
to CO Data Valid
t_DCSZ
Delay Time from CS High
to CO TRI-STATE
t_SCSC1
Setup Time, from CS Low to
CCLK Edge High
t_HCSC1
Hold Time, CS High from
CCLK Edge High
t_HCSC2
Hold Time, CS Low from
CCLK Edge High
t_SCSC2
Setup Time, CS High
to CCLK Edge High
t_CSH
t_DCI
Duration of CS High
Delay Time CS Low to
INT High-impedance
DIGITAL SYSTEM INTERFACE (See Figure 9)
F_BCK
t_BH,
t_BL
t_BR,
t_BF
t_FSa/b
t_SBC
Bit Clock Frequency
Clock Pulse Width
Hi & Low for BCLK
Rise and Fall Time
of BCLK
Frame Sync Frequency
Set up Time, B_x Valid
to BCLK Low
V_IH = 2.2V
V_IL = 0.7V
All Modes
t_HCB
Hold Time, B_x Valid
from BCLK Low
All Modes
t_DCD
Delay Time, BCLK Transition
to DTCK Transition
TEM, DCKE Mode
t_SDT
Setup Time, TxD Valid to
BCLK Low
TEM, DCKE Mode
t_HDT
Hold Time, BCLK Low to TxD
TEM, DCKE Mode
Invalid
25
Min
−100
20
Typ
15.36
Max
+100
50
10
Units
MHz
ppm
ns pk-pk
ns
ns
50
ns
50
ns
30
ns
20
ns
50
ns
50
ns
30
ns
30
ns
40
ns
50
ns
50
ns
1
µs
250
ns
256
4096
kHz
60
ns
15
ns
8
kHz
30
ns
20
ns
0
40
ns
30
ns
20
ns
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