ADC083000_09 Datasheet, PDF (25/40 Pages) National Semiconductor (TI) – 8-Bit, 3 GSPS, High Performance, Low Power A/D Converter

The ADC083000 will convert as long as the input clock signal
is present. The fully differential comparator design and the
innovative design of the sample-and-hold amplifier, together
with calibration, enables very good SINAD/ENOB response
beyond 1.5 GHz. The ADC083000 output data signaling is
LVDS and the output format is offset binary.
1.1.3 Control Modes
Much of the user control can be accomplished with several
control pins that are provided. Examples include initiation of
the calibration cycle, power down mode and full scale range
setting. However, the ADC083000 also provides an Extended
Control mode whereby a serial interface is used to access
register-based control of several advanced features. The Ex-
tended Control mode is not intended to be enabled and
disabled dynamically. Rather, the user is expected to employ
either the normal control mode or the Extended Control mode
at all times. When the device is in the Extended Control mode,
pin-based control of several features is replaced with register-
based control and those pin-based controls are disabled.
These pins are OutV (pin 3), OutEdge/DDR (pin 4), FSR (pin
14). See Section 1.2 for details on the Extended Control
mode.
1.1.4 The Analog Inputs
The ADC083000 must be driven with a differential input sig-
nal. Operation with a single-ended signal is not recommended
as performance will suffer. It is important that the input signals
are either a.c. coupled to the inputs with the V_CMO pin ground-
ed, or d.c. coupled with the V_CMO pin left floating or lightly
loaded. An input common mode voltage equal to the V_CMO
output must be provided when d.c. coupling is used.
Two full-scale range settings are provided with pin 14 (FSR).
A high on pin 14 causes an input full-scale range setting of
820 mV_P-P, while grounding pin 14 causes an input full-scale
range setting of 600 mV_P-P.
In the Extended Control mode, the full-scale input range can
be set to values between 560 mV_P-P and 840 mV_P-P through
a serial interface. See Section 2.2
1.1.5 Clocking
The ADC083000 sampling clock (CLK+/CLK-) must be driven
with an a.c. coupled, differential clock signal. Section 2.3 de-
scribes the use of the clock input pins. A differential LVDS
output clock (DCLK) is available for use in latching the ADC
output data into whatever device is used to receive the data.
The ADC083000 offers options for CLK+/CLK- and DCLK
clocking. For DCLK, the clock edge on which output data
transitions, and a choice of Single Data Rate (SDR) or Double
Data Rate (DDR) outputs are available.
The sampling clock CLK has optional duty cycle correction as
part of its circuit. This feature is enabled by default and pro-
vides improved ADC clocking. This circuitry allows the ADC
to be clocked with a signal source having a duty cycle of 80
to 20 % (worst case).
1.1.5.1 Output Demultiplexer
The ADC083000 utilizes both the rising and falling edge of the
input clock, resulting in the overall sample rate being twice the
input clock frequency or 3GSPS with a 1.5 GHz input clock.
The demultiplexer outputs data on each of the four output
busses at 750MHz with a 1.5GHz input clock.
All data is available in parallel at the output. The four bytes of
parallel data that are output with each clock is in the following
sampling order, from the earliest to the latest: Da, Db, Dc, Dd.
Table 1 indicates what the outputs represent for the various
sampling possibilities.
The ADC083000 includes an automatic clock phase back-
ground calibration feature which automatically and continu-
ously adjusts the phase of the ADC input clock. This feature
removes the need to manually adjust the clock phase and
provides optimal ENOB performance.
TABLE 1. Input Channel Samples Produced at Data Outputs
Data Outputs*
Dd
Db
Dc
Da
Input/Output Relationship
ADC1 sampled with the fall of CLK, 13 cycles earlier
ADC1 sampled with the fall of CLK, 14 cycles earlier
ADC2 sampled with the rise of CLK, 13.5 cycles earlier
ADC2 sampled with the rise of CLK, 14.5 cycles earlier
* Always sourced with respect to fall of DCLK
1.1.5.2 OutEdge Setting
To help ease data capture in the SDR mode, the output data
may be caused to transition on either the positive or the neg-
ative edge of the output data clock (DCLK). This is chosen
with the OutEdge input (pin 4). A high on the OutEdge input
pin causes the output data to transition on the rising edge of
DCLK+, while grounding this input causes the output to tran-
sition on the falling edge of DCLK+. See Section 2.4.3.
1.1.5.3 Double Data Rate
A choice of single data rate (SDR) or double data rate (DDR)
output is offered. When the device is in DDR mode, address
1h, bit 8 of the Configuration Register must be set to 0b. With
single data rate the output clock (DCLK) frequency is the
same as the data rate of the two output buses. With double
data rate the DCLK frequency is half the data rate and data
is sent to the outputs on both edges of DCLK. DDR clocking
is enabled in non-Extended Control mode by allowing pin 4 to
float.
1.1.6 The LVDS Outputs
The data outputs, Out Of Range (OR) and DCLK are LVDS.
Output current sources provide 3 mA of output current to a
differential 100 Ohm load when the OutV input (pin 3) is high
or 2.2 mA when the OutV input is low. For short LVDS lines
and low noise systems, satisfactory performance may be re-
alized with the OutV input low, which results in lower power
consumption. If the LVDS lines are long and/or the system in
which the ADC083000 is used is noisy, it may be necessary
to tie the OutV pin high.
The LVDS data outputs have a typical common mode voltage
of 800mV when the V_BG pin is floating. This common mode
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