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LM12454_06 Datasheet, PDF (24/36 Pages) National Semiconductor (TI) – 12-Bit + Sign Data Acquisition System with Self-Calibration | |||
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2.0 Internal User-Programmable
Registers
2.1 INSTRUCTION RAM
The instruction RAM holds up to eight sequentially execut-
able instructions. Each 48-bit long instruction is divided into
three 16-bit sections. READ and WRITE operations can be
issued to each 16-bit section using the instructionâs address
and the 2-bit âRAM pointerâ in the Configuration register. The
eight instructions are located at addresses 0000 through
0111 (A4âA1, BW = 0) when using a 16-bit wide data bus or
at addresses 00000 through 01111 (A4âA0, BW = 1) when
using an 8-bit wide data bus. They can be accessed and
programmed in random order.
Any Instruction RAM READ or WRITE can affect the se-
quencerâs operation:
The Sequencer should be stopped by setting the RESET
bit to a â1â or by resetting the START bit in the Configura-
tion Register and waiting for the current instruction to
finish execution before any Instruction RAM READ or
WRITE is initiated. Bit 0 of the Configuration Register
indicates the Sequencer Status. See paragraph 2.2 for
information on the Configuration Register.
A soft RESET should be issued by writing a â1â to the
Configuration Registerâs RESET bit after any READ or
WRITE to the Instruction RAM.
The three sections in the Instruction RAM are selected by
the Configuration Registerâs 2-bit âRAM Pointerâ, bits D8 and
D9. The first 16-bit Instruction RAM section is selected with
the RAM Pointer equal to â00â. This section provides multi-
plexer channel selection, as well as resolution, acquisition
time, etc. The second 16-bit section holds âwatchdogâ limit
#1, its sign, and an indicator that shows that an interrupt can
be generated if the input signal is greater or less than the
programmed limit. The third 16-bit section holds âwatchdogâ
limit #2, its sign, and an indicator that shows that an interrupt
can be generated if the input signal is greater or less than the
programmed limit.
Instruction RAM â00â
Bit 0 is the LOOP bit. It indicates the last instruction to be
executed in any instruction sequence when it is set to a â1â.
The next instruction to be executed will be instruction 0.
Bit 1 is the PAUSE bit. This controls the Sequencerâs opera-
tion. When the PAUSE bit is set (â1â), the Sequencer will stop
after reading the current instruction and before executing it,
and the start bit in the Configuration register is automatically
reset to a â0â. Setting the PAUSE also causes an interrupt to
be issued. The Sequencer is restarted by placing a â1â in the
Configuration registerâs Bit 0 (Start bit).
After the Instruction RAM has been programmed and the
RESET bit is set to â1â, the Sequencer retrieves Instruction
000, decodes it, and waits for a â1â to be placed in the
Configurationâs START bit. The START bit value of â0â âover-
ridesâ the action of Instruction 000âs PAUSE bit when the
Sequencer is started. Once started, the Sequencer executes
Instruction 000 and retrieves, decodes, and executes each
of the remaining instructions. No PAUSE Interrupt (INT 5) is
generated the first time the Sequencer executes Instruction
000 having a PAUSE bit set to â1â. When the Sequencer
encounters a LOOP bit or completes all eight instructions,
Instruction 000 is retrieved and decoded. A set PAUSE bit in
Instruction 000 now halts the Sequencer before the instruc-
tion is executed.
Bits 2â4 select which of the eight input channels (â000â to
â111â for IN0âIN7) will be configured as non-inverting inputs
to the LM12(H)458âs ADC. (See Table 1.) They select which
of the four input channels (â000â to â011â for IN0âIN4) will be
configured as non-inverting inputs to the LM12454âs ADC.
(See Table 2.)
Bits 5â7 select which of the seven input channels (â001â to
â111â for IN1 to IN7) will be configured as inverting inputs to
the LM12(H)458âs ADC. (See Table 1.) They select which of
the three input channels (â001â to â011â for IN1âIN4) will be
configured as inverting inputs to the LM12454âs ADC. (See
Table 2.) Fully differential operation is created by selecting
two multiplexer channels, one operating in the non-inverting
mode and the other operating in the inverting mode. A code
of â000â selects ground as the inverting input for single
ended operation.
Bit 8 is the SYNC bit. Setting Bit 8 to â1â causes the Se-
quencer to suspend operation at the end of the internal S/Hâs
acquisition cycle and to wait until a rising edge appears at
the SYNC pin. When a rising edge appears, the S/H ac-
quires the input signal magnitude and the ADC performs a
conversion on the clockâs next rising edge. When the SYNC
pin is used as an input, the Configuration registerâs âI/O
Selectâ bit (Bit 7) must be set to a â0â. With SYNC configured
as an input, it is possible to synchronize the start of a
conversion to an external event. This is useful in applications
such as digital signal processing (DSP) where the exact
timing of conversions is important.
When the LM12(H)454/8 are used in the âwatchdogâ mode
with external synchronization, two rising edges on the SYNC
input are required to initiate two comparisons. The first rising
edge initiates the comparison of the selected analog input
signal with Limit #1 (found in Instruction RAM â01â) and the
second rising edge initiates the comparison of the same
analog input signal with Limit #2 (found in Instruction RAM
â10â).
Bit 9 is the TIMER bit. When Bit 9 is set to â1â, the Se-
quencer will halt until the internal 16-bit Timer counts down
to zero. During this time interval, no âwatchdogâ comparisons
or analog-to-digital conversions will be performed.
Bit 10 selects the ADC conversion resolution. Setting Bit 10
to â1â selects 8-bit + sign and when reset to â0â selects 12-bit
+ sign.
Bit 11 is the âwatchdogâ comparison mode enable bit. When
operating in the âwatchdogâ comparison mode, the selected
analog input signal is compared with the programmable
values stored in Limit #1 and Limit #2 (see Instruction RAM
â01â and Instruction RAM â10â). Setting Bit 11 to â1â causes
two comparisons of the selected analog input signal with the
two stored limits. When Bit 11 is reset to â0â, an 8-bit + sign
or 12-bit + sign (depending on the state of Bit 10 of Instruc-
tion RAM â00â) conversion of the input signal can take place.
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