EM6605 Datasheet, PDF (22/43 Pages) National Semiconductor (TI) – 4 bit Microcontroller

EM6605
11.Serial (Output) Write Buffer - SWB
The EM6605 has simple Serial Write Buffer (SWB) which outputs serial data and serial clock.
The SWB is enabled by setting the bit V03 in the CLKSWB register as well as setting port D to output mode. The
combination of the possible PortD mode is shown in Table 357. In SWB mode the serial clock is output on port
D0 and the serial data is output on port D1.
The signal TestVar[3], which is used by the processor to make conditional jumps, indicates "Transmission
finished" in automatic send mode or "SWBbuffer empty" in interactive send mode. In interactive mode,
TestVar[3] is equivalent to the interrupt request flags stored in IntRq register : it permits to recognize the
interrupt source. (See also the interrupt handling section 9.Interrupt Controller for further information). To serve
the "SWBbuffer empty " interrupt request, one only has to make a conditional jump on TestVar[3].
The Serial Write Buffer output clock frequency is selected by bits ClkSWB0 and ClkSWB1 in the ClkSWB
register. The possible values are 1kHz (default), 2kHz, 8kHz or 16kHz and are shown in Table 35.
Table 36.SWB clock selection
SWB clock output
ck[11]; (= 1 024 Hz *f1)
ck[12]; (= 2 048 Hz *f1)
ck[14]; (= 8 192 Hz *f1)
ck[15]; (= 16 348 Hz *f1)
CkSWB1
0
0
1
1
CkSWB0
0
1
0
1
Table 376.SWB clock selection register - ClkSWB
Bit
Name
Reset
R/W
3
V03
0
R/W
2
-
0
R
1
CkSWB1
0
R/W
0
CkSWB0
0
R/W
Description
Serial Write buffer selection
RESERVED - read 0
SWB clock selector 1
SWB clock selector 0
Table 387.PortD status
PortD status
« NORMAL »
« NORMAL »
« NORMAL »
« SWB »
CIOPD
0
0
1
1
V03 PD0
0 input
1 input
0 output PD0
1 serial clock Out
PD1
input
input
output PD1
SWB serial data
PD2
input
input
output PD2
output PD2
PD3
input
input
output PD3
output PD3
When the SWB is enabled by setting the bit V03 TestVar[3], which is used to make conditional jumps, is
reassigned to the SWB and indicates either "SWBbuffer empty " interrupt or "Transmission finished" . After
Power-on-RESET V03 is cleared at "0" and TestVar[3] is consequently assigned to PA2 input terminal.
The SWB data is output on the rising edge of the clock. Consequently, on the receiver side the serial data can be
evaluated on falling edge of the serial clock edge.
© EM Microelectronic-Marin SA, 02/99, Rev. B/243
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