ADCS9888_05 Datasheet, PDF (22/34 Pages) National Semiconductor (TI) – 205/170/140 MSPS Video Analog Front End

Configuration Register Descriptions (Continued)
Address Write/Read Bits
(Hex) or Read Only
15H
W/R
7
6
5
4
3
2:1
0
16H
W/R
7:0
17H
W/R
7:0
18H
RO
7:0
19H
RO
7:0
POR Value
Name
Bit Name/Description
1*******
*1******
**0*****
***0****
****0***
*****11*
*******0
11111111
00000000
Channel Mode
Output Mode
A/B Even/Odd
4:2:2 Output
Mode
Input Mux
Input
Bandwidth
External Clock
Test Register
Test Register
Test Register
Test Register
Sets the channel mode of the data outputs. 0 = single
channel mode. 1 = dual channel mode. In dual channel
mode, the DATACK output clocks operate at 1/2 of the
pixel conversion rate, and pixel data is updated on the
A and B output ports. See also Register 15H, bit 6.
Sets the output mode of the data outputs. 0 =
interleaved mode, 1 = parallel mode. In interleaved
mode, one output port is updated on the rising edge of
DATACK, the other output port is updated on the falling
edge of DATACK.
When this bit is set to 1, HSOUT transitions on the
rising edge of DATACK. (Instead of the falling edge as
shown in the timing diagrams).
Selects 4:2:2 subsampled output formatting mode, for
use with YUV type video signals. 0 = normal output
formatting, 1 = 4:2:2 output formatting.
In YUV 4:2:2 mode, the channel connections and data
output are as follows:
Channel
Input Signal
Output
Red
V
U/V
Green
Y
Y
Blue
U
High Z
Selects which video input source is used. 0 = port 0, 1
= port 1.
Sets the analog input bandwidth.
11 = 500 MHz
10 = 300 MHz
01 = 150 MHz
00 = 75 MHz
Determines whether the internal Hsync referenced PLL
is used as the clock source, or the CKEXT source is
used. 0 = internal PLL. 1 = CKEXT is used.
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