THS770012 Datasheet, PDF (21/35 Pages) Texas Instruments – Broadband, Fully-Differential, 14-/16-Bit ADC Driver Amplifier

THS770012
www.ti.com
SLOS669C – FEBRUARY 2010 – REVISED JANUARY 2012
SFDR Considerations
Theoretically, the spurious-free dynamic range (SFDR) of the amplifier + filter + ADC adds linearly on a
spur-by-spur basis. The amplifier output spurs are linearly related solely to the input signal and the SFDR is
usually set by second-order or third-order harmonic distortion for single-tone inputs, and by second-order or
third-order intermodulation distortion for two-tone inputs. Harmonic and second-order intermodulation distortion
can be filtered to some degree by the antialias filter, but not third-order intermodulation distortion. Generally, the
ADC also has the same distortion products, but as a result of the sampling nature and potential for clock
feedthrough, there may be spurs not linearly related solely to the input signal. When the spurs from the amplifier
+ filter are known, each can be directly added to the same spur from the ADC. This is a worst-case analysis
based on the assumption the spurs sources are in phase. If the spur of the amplifier + filter equals the spur of the
ADC, the combined spur is 6dB higher. The combined spur calculated in this manner is usually accurate to within
±6dB of actual implementation, but higher variations have been observed especially in second-order
performance as a result of phase shift in the filter.
Common-mode phase shift introduced by the filter nullifies the basic assumption that the spur sources are in
phase. This phase shift can lead to better performance than predicted as the spurs become phase shifted, and
there is the potential for cancellation as the phase shift reaches 180°.
Differential phase and magnitude imbalance in the filter as a result of mismatched components caused by
nominal tolerance can severely degrade the second-order distortion of the ADC. Single-order RC filters cause
very little differential phase shift with nominal tolerances of 5% or less, but higher-order LC filters are very
sensitive to component mismatch. For instance, a third-order Butterworth bandpass filter with 100MHz center
frequency and 20MHz bandwidth shows up to 20° differential phase imbalance in a Spice Monte Carlo analysis
with 2% component tolerances. Therefore, while a prototype may work, production variance is unacceptable. Low
tolerance 1% components and low order filter is recommended for best performance. Otherwise a transformer or
balun is recommended at the ADC input to restore the phase balance in the input signal to the ADC.
ADC Input Common-Mode Voltage Considerations
The input common-mode voltage range of the ADC must be observed for proper operation. In an ac-coupled
application between the amplifier and the ADC, the input common-mode voltage bias of the ADC is
accomplished in different ways depending on the ADC. Some use internal bias networks and others use external
components, such as resistors, from each input to the CM output of the ADC. When ac coupling, the output
common-mode voltage of the amplifier is a don’t care for the ADC, and V_OCM should be set for optimum
performance of the amplifier.
DC-coupled applications vary in complexity and requirements, depending on the ADC. Devices such as the
ADS5424 require a nominal 2.4V input common-mode, while others such as the ADS5485 require a nominal
3.1V input common-mode, and still others like the ADS6149 require 1.5V and the ADS4149 require 0.95V. Given
the THS770012 output common-mode range, ADCs with input common-mode closer to 2.5V are easier to
dc-couple to, and require little or no level shifting. For applications that require a different common-mode voltage
between the amplifier and the ADC, a resistor network can be used, as shown in Figure 41. With ADCs that have
internal resistors (R_INT) that bias the ADC input to V_CM, the bias resistors do not affect the desired value of R_P,
but do cause more attenuation of the differential input signal. Knowing the differential input resistance is required
and sometimes, that is all that is provided.
V_REF
V_AMP+
R_O
R_P
V_ADC+
ADC
Amp
R_IN
C_IN
V_AMP-
R_O
R_P
V_ADC-
V_REF
Figure 41. Resistor Network to DC Level Shift Common-Mode Voltage
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