DS90C387 Datasheet, PDF(21/26 Page) National Semiconductor (TI) – Dual Pixel LVDS Display Interface (LDI)-SVGA/QXGA

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DS90C387 Datasheet, PDF (21/26 Pages) National Semiconductor (TI) – Dual Pixel LVDS Display Interface (LDI)-SVGA/QXGA

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Applications Information

HOW TO CONFIGURE THE DS90C387 AND DS90CF388

FOR MOST COMMON APPLICATION

1. To configure for single input pixel-to-dual pixel output

application, the DS90C387 âDUALâ pin must be set to 1/2

Vcc=1.65V. This may be implemented using pull-up and

pull-down resistors of 10kâ¦ each as shown in Figure 16. A

capacitor between âDUALâ pin and ground will help to stabi-

lize the DC voltage level in a noisy environment. In this

configuration, the input signals (single pixel) are split into

odd and even pixel (dual pixels) starting with the odd (first)

pixel outputs A0-to-A3 the next even (second) pixel outputs

to A4-to-A7. The splitting of the data signal also starts with

DE (data enable) transitioning from logic low to high indicat-

ing active data. The "R_FDE" pin must be set high in this

case. This is supported in DC Balanced and non-DC Bal-

anced (BAL=low or high) data transmission. The number of

clock cycles during blanking must be an EVEN number. This

configuration will allow the user to interface to an LDI re-

ceiver (DS90CF388) or if in the non-DC Balanced mode

(BAL=low) then two FPD-Link ânotebookâ receivers

(DS90CF384A). The DC Balance feature is recommended

for monitor applications which require >2meters of cable

length. Notebook applications should disable this feature to

reduce the current consumption of the chipset. Note that

only the DS90C387/DS90CF388 support the DC Balance

data transmission feature.

2. To configure for single pixel or dual pixel application using

the DS90C387/DS90CF388, the âDUALâ pin must be set to

Vcc (dual) or Gnd (single). In dual mode, the transmitter-

DS90C387 has two LVDS clock outputs enabling an inter-

face to two FPD-Link ânotebookâ receivers (DS90CF384A or

DS90CF386). In single mode, outputs A4-to-A7 and CLK2

are disabled which reduces power dissipation. Both single

and dual mode also support the DC Balance data transmis-

sion feature, which should only be used for monitor applica-

tion.

The DS90CF388 is able to support single or dual pixel

interface up to 112MHz operating frequency. This receiver

may also be used to interface to a VGA controller with an

integrated LVDS transmitter without DC Balance data trans-

mission. In this case, the receivers âBALâ pin must be tied

low (DC Balance disabled).

NEW FEATURES DESCRIPTION

Pre-emphasis

adds extra current during LVDS logic transition to reduce the

cable loading effects. Pre-emphasis strength is set via a DC

voltage level applied from min to max (0.75V to Vcc) at the

âPREâ pin. A higher input voltage on the âPREâ pin increases

the magnitude of dynamic current during data transition. The

âPREâ pin requires one pull-up resistor (Rpre) to Vcc in order

to set the DC level. There is an internal resistor network,

which cause a voltage drop. Please refer to the tables below

to set the voltage level.

TABLE 5. PRE-EMPHASIS DC VOLTAGE LEVEL WITH (RPRE)

Rpre

1Mâ¦ or NC

50kâ¦

9kâ¦

3kâ¦

1kâ¦

100â¦

Resulting PRE Voltage

0.75V

1.0V

1.5V

2.0V

2.6V

Vcc

Effects

Standard LVDS

50% pre-emphasis

100% pre-emphasis

TABLE 6. PRE-EMPHASIS NEEDED PER CABLE LENGTH

Frequency

112MHz

80MHz

65MHz

56MHz

PRE Voltage

1.0V

1.5V

1.0V

1.2V

1.5V

1.0V

Typical cable length

2 meters

5 meters

2 meters

7 meters

10 meters

Note 20: This is based on testing with standard shield twisted pair cable. The amount of pre-emphasis will vary depending on the type of cable, length and operating

frequency.

DC Balance

In the Balanced operating modes, in addition to pixel and

control information an additional bit is transmitted on every

LVDS data signal line during each cycle of active data as

shown inFigure 18 . This bit is the DC Balance bit (DCBAL).

The purpose of the DC Balance bit is to minimize the short-

and long-term DC bias on the signal lines. This is achieved

by selectively sending the pixel data either unmodified or

inverted.

The value of the DC Balance bit is calculated from the

running word disparity and the data disparity of the current

word to be sent. The data disparity of the current word shall

be calculated by subtracting the number of bits of value 0

from the number of bits value 1 in the current word. Initially,

the running word disparity may be any value between +7 and

â6. The running word disparity shall be calculated as a

continuous sum of all the modified data disparity values,

where the unmodified data disparity value is the calculated

data disparity minus 1 if the data is sent unmodified and 1

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