CP3CN17 Datasheet, PDF (209/220 Pages) National Semiconductor (TI) – Reprogrammable Connectivity Processor with CAN Interface

26.13 EXTERNAL BUS TIMING
Table 78 External Bus Signals
Symbol Figure
Description
Reference
External Bus Input Signals
109,
t₁
111, Input Setup Time
112, D[15:0]
113
109,
t₂
111, Output Hold Time
112, D[15:0]
113
Before Rising Edge (RE)
on CLK
After RE on CLK
External Bus Output Signals
t₃
109, Output Valid Time
110 D[15:0]
109,
110, Output Valid Time
t₄ 111, A[21:0] (CP3BT10)
112, A[22:0] (CP3BT13)
113
t₅
109,
110,
111,
112,
113
Output Active/Inactive Time
RD
SEL[1:0]
SELIO
t₆
109, Output Active/Inactive Time
110 WR[1:0]
t₇
111
Minimum Inactive Time
RD
t₈
109
Output Float Time
D[15:0]
t₉
109 Minimum Delay Time
t₁₀
109,
110
Minimum Delay Time
t₁₁ 110 Minimum Delay Time
Output Hold Time
109, A22 (CP3BT13 only)
110, A[21:0]
t₁₂ 111, D[15:0]
112, RD
113 SEL[2:0]
SELIO
t₁₃
109, Output Hold Time
110 WR[1:0]
After RE on CLK
After RE on CLK
After RE on CLK
After RE on CLK
At 2.0V
After RE on CLK
From RD Trailing Edge
(TE) to D[15:0] driven
From RD TE to SELn
Leading Edge (LE)
From SELx TE to SELy LE
After RE on CLK
After RE on CLK
Min (ns)
8
0
-
-
-
-
Tclk - 4
-
Tclk - 4
0
0
0
0.5 Tclk - 3
Max (ns)
-
-
8
8
8
0.5 Tclk + 8
-
8
-
-
-
-
-
209
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