LMP7312_14 Datasheet, PDF (20/29 Pages) National Semiconductor (TI) – Precision SPI-Programmable AFE with Differential/Single-Ended Input/Output

LMP7312
SNOSB32B – MARCH 2010 – REVISED MARCH 2013
www.ti.com
V_IO
R_1N
-V_IN
R_2N
-IN
V⁺
R_FP
-
+V_OUT
+IN
R_2P
+V_IN
R_1P
+
V⁺
R_FN
100 k:
-V_OUT/V_R
V_OCM
100 k:
V^-
V^-
Figure 38. LMP7312 in High Impedance Mode
In each case the SPI registers require 5 bits. The table below is a summary of all allowed configurations.
MSB
Gain_1
0
0
1
1
1
1
x
x
Gain_0
0
1
0
1
0
1
x
x
EN_CL
0
0
0
0
1
1
x
x
Null_SW
0
0
0
0
0
0
x
1
LSB
Hi_Z
0
0
0
0
0
0
1
0
Gain Value (V/V)
0.096
0.192
0.384
0.768
1
2
–
1
Mode of Operation
Attenuation Mode
Attenuation Mode
Attenuation Mode
Attenuation Mode
Amplification Mode
Amplification Mode
High Impedance Output
Null Switch Mode
Daisy Chain
The LMP7312 supports daisy chaining of the serial data stream between multiple chips. To use this feature serial
data is clocked into the first chip SDI pin, and the next chip SDI pin is connected to the SDO pin of the first chip.
Both chips may share a chip select signal, or the second chip can be enabled separately. When the chip select
pin goes low on both chips and 5 bits have been clocked into the first chip the next 5 clock cycle begins moving
new configuration data into the second chip. With a full 10 clock cycles both chips have valid data and the chip
select pin of both chips should be brought high to prevent the data from overshooting.
20
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