LM4934 Datasheet, PDF (20/39 Pages) National Semiconductor (TI) – 3D Audio Sub-System with Stereo Speaker, OCL/SE Stereo Headphone, Earpiece and Mono Line Level Outputs

PLL Configuration Registers (Continued)
PLL N Modulator and Dither Select Configuration Register
This register is used to control the Fractional component of the PLL.
PLL_N_MOD (0Ch) (Set = logic 1, Clear = logic 0)
Bits
Register
Description
4:0
PLL_N_MOD
This programs the PLL N Modulator’s fractional component:
PLL_N_MOD
Fractional Addition
0
0/32
1
1/32
2 → 30
2/32 → 30/32
31
31/32
6:5
DITHER_LEVEL
Allows control over the dither used by the N Modulator
DITHER_LEVEL
DAC Sub-system Input Source
00
Medium (32)
01
Small (16)
10
Large (48)
11
Off
7
FAST_VCO
If set the VCO maximum and minimum frequencies are raised:
FAST_VCO
0
Maximum F_VCO
40–55MHz
1
55–80MHz
NOTES:
The complete N divider is a fractional divider as such:
N = PLL_N + (PLL_N_MOD/32)
If the modulus input is zero, then the N divider is simply an integer N divider. The output from the PLL is determined by the following formula:
Fout = (Fin * N) / (M * P)
Please see over for more details on the PLL and common settings.
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