ADC082500 Datasheet, PDF (20/33 Pages) National Semiconductor (TI) – High Performance, Low Power, 8-Bit, 2.5 GSPS A/D Converter

1.0 Functional Description (Continued)
controls are disabled. These pins are OutV (pin 3), OutEdge/
DDR (pin 4), FSR (pin 14). See Section 1.2 for details on the
Extended Control mode.
1.1.4 The Analog Inputs
The ADC082500 must be driven with a differential input
signal. Operation with a single-ended signal is not recom-
mended. It is important that the input signals are either a.c.
coupled to the inputs with the V_CMO pin grounded, or d.c.
coupled with the V_CMO pin left floating. An input common
mode voltage equal to the V_CMO output must be provided
when d.c. coupling is used.
Two full-scale range settings are provided with pin 14 (FSR).
A high on pin 14 causes an input full-scale range setting of
870 mV_P-P, while grounding pin 14 causes an input full-scale
range setting of 650 mV_P-P. The full-scale range setting
operates equally on both ADCs.
In the Extended Control mode, the full-scale input range can
be set to values between 560 mV_P-P and 840 mV_P-P through
a serial interface. See Section 2.2
1.1.5 Clocking
The ADC082500 must be driven with an a.c. coupled, differ-
ential clock signal. Section 2.3 describes the use of the clock
input pins. A differential LVDS output clock is available for
use in latching the ADC output data into whatever device is
used to receive the data.
The ADC082500 offers options for input and output clocking.
These options include a choice of on which DCLK (DCLK)
edge the output data transitions, and a choice of Single Data
Rate (SDR) or Double Data Rate (DDR) outputs.
The ADC082500 also has the option to use a duty cycle
corrected clock receiver as part of the input clock circuit. This
feature is enabled by default and provides improved ADC
clocking. This circuitry allows the ADC to be clocked with a
signal source having a duty cycle ratio of 80 / 20 % (worst
case).
1.1.5.1 Selectable Output Demultiplexer
The ADC082500 utilizes both the rising and falling edge of
the input clock resulting in the overall sample rate being
twice the input clock frequency, or 2.5 GSPS with a 1.25
GHz input clock. To ease the timing requirements of a sys-
tem interfacing to the ADC output ports, a selectable output
demultiplexer is provided. The demultiplexer selection is
programmed in the extended control mode using the Con-
figuration Register. Refer to section 1.4. The default setting
selects the 1:4 demultiplexer with data on each of the four
output busses at 625 MHz with a 1.25GHz input clock. When
Bit 0 in the Configuration Register is programmed to 1b, the
data is present on Dc and Dd output busses at a rate of 1.25
GHz with a 1.25 GHz input clock. NOTE: Bit 0 can only be
programmed 1b when the ADC082500 is in DDR mode. If
the device is not in DDR mode and Bit 0 is set to 1b, the data
outputs will not change.
All data is available in parallel at the output. The four bytes of
parallel data that are output with each clock is in the follow-
ing sampling order, from the earliest to the latest: Da, Db, Dc,
Dd. Table 1 indicates what the outputs represent for the
various sampling possibilities.
The ADC082500 includes an automatic clock phase back-
ground calibration feature which automatically and continu-
ously adjusts the phase of the ADC input clock. This feature
removes the need to manually adjust the clock phase and
provides optimal ENOB performance.
TABLE 1. Input Channel Samples Produced at Data Outputs
Data Outputs (Always sourced
with respect to fall of DCLK)
Dd
Db
Dc
Da
1:4 Demultiplex
ADC1 sampled with fall of CLK 13
cycles earlier
ADC1 sampled with fall of CLK 14
cycles earlier
ADC2 sampled with rise of CLK 13.5
cycles earlier
ADC2 sampled with rise of CLK 14.5
cycles earlier
1:2 Demultiplex
ADC1 sampled with fall of CLK 13 cycles
earlier
ADC2 sampled with rise of CLK 13.5
cycles earlier
1.1.5.2 OutEdge Setting
To help ease data capture in the SDR mode, the output data
may be caused to transition on either the positive or the
negative edge of the output data clock (DCLK). This is
chosen with the OutEdge input (pin 4). A high on the Out-
Edge input pin causes the output data to transition on the
rising edge of DCLK, while grounding this input causes the
output to transition on the falling edge of DCLK. See Section
2.4.3.
1.1.5.3 Double Data Rate
A choice of single data rate (SDR) or double data rate (DDR)
output is offered. With single data rate the output clock
(DCLK) frequency is the same as the data rate of the two
output buses. With double data rate the DCLK frequency is
half the data rate and data is sent to the outputs on both
edges of DCLK. DDR clocking is enabled in non-Extended
Control mode by allowing pin 4 to float.
1.1.6 The LVDS Outputs
The data outputs, the Out Of Range (OR) and DCLK, are
LVDS. Output current sources provide 3 mA of output current
to a differential 100 Ohm load when the OutV input (pin 14)
is high or 2.2 mA when the OutV input is low. For short LVDS
lines and low noise systems, satisfactory performance may
be realized with the OutV input low, which results in lower
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