TP5510 Datasheet, PDF(2/12 Page) National Semiconductor (TI) – Full Duplex Analog Front End for Consumer Applications

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TP5510 Datasheet, PDF (2/12 Pages) National Semiconductor (TI) – Full Duplex Analog Front End for Consumer Applications

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Block Diagram

FIGURE 1

TL H 11186 â 2

Pin Description

Symbol

VBB

GNDA

VFDO

VCC

Function

Negative power supply pin VBB e b5V

g5%

Analog ground All signals are referenced

to this pin

Analog output of the receive power ampli-

fier

Positive power supply pin VCC e a5V

g5%

Symbol

Function

FSD

Decode frame sync pulse which enables

BCLKR to shift data into DD FSD is an

8 kHz pulse train See Figures 2 and 3 for

timing details

Decode data input Data is shifted into DD

following the FSD leading edge

BCLKD CLKSEL The bit clock which shifts data into DD af-

ter the FSD leading edge May vary from

64 kHz to 2 048 MHz Alternatively may

be a logic input which selects either

1 536 MHz 1 544 MHz or 2 048 MHz for

master clock in synchronous mode and

BCLKD is used for both encode and de-

code directions (see Table 1)

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