LP339 Datasheet, PDF (2/11 Pages) National Semiconductor (TI) – Ultra-Low Power Quad Comparator

Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
Differential Input Voltage
Input Voltage
Power Dissipation (Note 2)
Molded DIP
Output Short Circuit to GND (Note 3)
Input Current V_IN<−0.3 V_DC (Note 4)
36 V_DC or ±18 V_DC
±36 V_DC
−0.3 V_DC to 36 V_DC
570 mW
Continuous
50 mA
Operating Temperature Range
0˚C to +70˚C
Storage Temperature Range
−65˚ to +150˚C
Soldering Information:
Dual-In-Line Package (10 sec.)
+260˚C
S.O. Package:
Vapor Phase (60 sec.)
+215˚C
Infrared (15 sec.)
+220˚C
See AN-450 “Surface Mounting Methods and Their Effect on
Product Reliability” for other methods of soldering surface
mount devices.
Electrical Characteristics
(V+=5 V_DC) (Note 5)
Parameter
Conditions
Min Typ
Max
Units
Input Offset Voltage
Input Bias Current
Input Offset Current
Input Common
Mode Voltage Range
T_A=25˚C (Note 10)
I_IN(+) or I_IN(−) with the
Output in the Linear Range, T_A=25˚C (Note 6)
I_IN(+)−I_IN(−), T_A=25˚C
T_A=25˚C (Note 7)
±2
±5
mV_DC
2.5
25
nA_DC
±0.5
±5
nA_DC
0
V+−1.5
V_DC
Supply Current
Voltage Gain
Large Signal
Response Time
Response Time
Output Sink Current
Output Leakage Current
Input Offset Voltage
Input Offset Current
Input Bias Current
Input Common
Mode Voltage Range
R_L=Infinite on all Comparators, T_A=25˚C
V_O = 1 V_DC to 11 V_DC,
R_L=15 kΩ, V⁺=15 V_DC, T_A=25˚C
V_IN=TTL Logic Swing, V_REF=1.4 V_DC,
V_RL=5 V_DC, R_L=5.1 kΩ, T_A=25˚C
V_RL=5 V_DC, R_L=5.1 kΩ, T_A=25˚C (Note 8)
V_IN(−)=1 V_DC, V_IN(+)=0, V_O=2 V_DC,
T_A=25˚C (Note 12)
V_O=0.4 V_DC
V_IN(+)=1 V_DC, V_IN(−)=0, V_O=5 V_DC, T_A=25˚C
(Note 10)
I_IN(+)−I_IN(−)
I_IN(+) or I_IN(−) with Output in Linear Range
Single Supply
60
100
µA_DC
500
V/mV
1.3
µSec
8
15
30
µSec
mA_DC
0.20
0
0.70
0.1
±1
4
±9
±15
40
V+−2.0
mA_DC
nA_DC
mV_DC
nA_DC
nA_DC
V_DC
Output Sink Current
V_IN(−)=1 V_DC, V_IN(+)=0, V_O=2 V_DC
10
Output Leakage Current
V_IN(+)=1 V_DC, V_IN(−)=0, V_O=30 V_DC
Differential Input Voltage
All V_IN’s≥0 V_DC (or V^− on split supplies) (Note 9)
mA_DC
1.0
µA_DC
36
V_DC
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is func-
tional, but do not guarantee specific performance limits.
Note 2: For elevated temperature operation, T_j max is 125˚C for the LP339. θ_ja (junction to ambient) is 175˚C/W for the LP339N and 120˚C/W for the LP339M when
either device is soldered in a printed circuit board in a still air environment. The low bias dissipation and the “ON-OFF” characteristic of the outputs keeps the chip
dissipation very small (P_D ≤ 100 mW), provided the output transistors are allowed to saturate.
Note 3: Short circuits from the output to V⁺ can cause excessive heating and eventual destruction. The maximum output current is approximately 50 mA.
Note 4: This input current will only exist when the voltage at any of the input leads is driven negative. It is due to the collector-base junction of the input PNP tran-
sistors becoming forward biased and thereby acting as input clamp diodes. In addition to this diode action, there is also lateral NPN parasitic transistor action on the
IC chip. This transistor action can cause the output voltage of the comparators to go to the V+ voltage level (or to ground for a large input overdrive) for the time du-
ration that an input is driven negative. This is not destructive and normal output states will re-establish when the input voltage, which is negative, again returns to a
value greater than −0.3 V_DC (T_A=25˚C).
Note 5: These specifications apply for V⁺=5V_DC and 0˚C≤T_A≤70˚ C, unless otherwise stated. The temperature extremes are guaranteed but not 100% production
tested. These parameters are not used to calculate outgoing AQL.
Note 6: The direction of the input current is out of the IC due to the PNP input stage. This current is essentially constant, independent of the state of the output, so
no loading change exists on the reference or the input lines as long as the common-mode range is not exceeded.
Note 7: The input common-mode voltage or either input voltage should not be allowed to go negative by more than 0.3V. The upper end of the common-mode volt-
age range is V⁺−1.5V (T_A=25˚C), but either or both inputs can go to 30 V_DC without damage.
Note 8: The response time specified is for a 100 mV input step with 5 mV overdrive. For larger overdrive signals 1.3 µs can be obtained. See Typical Performance
Characteristics section.
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