LM34923 Datasheet, PDF (2/12 Pages) National Semiconductor (TI) – EVAL evaluation board provides the design engineer with a fully

Board Layout and Probing
The pictorial in Figure 1 shows the placement of the circuit
components. The following should be kept in mind when the
board is powered:
1) When operating at high input voltage and high load current,
forced air flow may be necessary.
2) The LM34923 may be hot to the touch when operating at
high input voltage and high load current.
3) Use CAUTION when probing the circuit at high input volt-
ages to prevent injury, as well as possible damage to the
circuit.
4) At maximum load current, the wire size and length used to
connect the load becomes important. Ensure there is not a
significant drop in the wires between this evaluation board
and the load.
Board Connection/Start-up
The input connections are made to the J1 connector. The load
is connected to the J2 (OUT) and J3 (GND) terminals. Ensure
the wires are adequately sized for the intended load current.
Before start-up a voltmeter should be connected to the input
terminals, and to the output terminals. The load current should
be monitored with an ammeter or a current probe. It is rec-
ommended that the input voltage be increased gradually to
6V, at which time the output voltage should be 5V. If the output
voltage is correct with 6V at VIN, then increase the input volt-
age as desired and proceed with evaluating the circuit. DO
NOT EXCEED 75V AT VIN.
Output Ripple Control
The LM34923 requires a minimum of 25 mVp-p ripple at the
FB pin, in phase with the switching waveform at the SW pin,
for proper operation. The required ripple can be supplied from
ripple at V_OUT, through the feedback resistors as described in
Option A below. Options B and C provide lower output ripple
with one or two additional components.
Option A) Lowest Cost Configuration: In this configuration
R7 is installed in series with the output capacitance (C2).
Since ≥25 mVp-p are required at the FB pin, R7 must be
chosen to generate ≥50 mVp-p at V_OUT, knowing that the
minimum ripple current in this circuit is ≊51 mAp-p at mini-
mum V_IN. Using 1Ω for R7, the ripple at V_OUT ranges from
≊51 mVp-p to ≊280 mVp-p over the input voltage range. If the
application can accept this ripple level, this is the most eco-
nomical solution. The circuit is shown in Figure 2. See Figure
8. R8, C6, C7, and C8 are not used in this configuration.
FIGURE 2. Lowest Cost Configuration
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