DS90C3201 Datasheet, PDF (2/3 Pages) National Semiconductor (TI) – 3.3V 8 MHz to 135 MHz Dual FPD-Link Transmitter

Typical Application Diagram
FIGURE 2. LCD Panel Application Diagram
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Functional Description
The DS90C3201 and DS90C3202 are a dual 10-bit color
Transmitter and Receiver FPD-Link chipset designed to
transmit data at clocks speeds from 8 to 135 MHz.
DS90C3201 and DS90C3202 are designed to interface be-
tween the digital video processor and the display using a
LVDS interface. The DS90C3201 transmitter serializes 2
channels of video data (10-bit each for RGB for each chan-
nel, totaling 60 bits) and control signals (HSYNC, VSYNC,
DE and two user-defined signals) along with clock signal to
10 channels of LVDS signals and transmits them. The
DS90C3202 receiver converts 10 channels of LVDS signals
into parallel signals and outputs 2 channels of video data
(10-bit each for RGB for each channel, totaling 60 bits) and
control signals (HSYNC, VSYNC, DE and two user-defined
signals) along with clock signal. The dual high speed LVDS
channels supports single pixel in-single pixel out and dual
pixel in-dual pixel out transmission modes. The FPD-Link
chipset is suitable for a variety of display applications includ-
ing LCD Monitors, LCD TV, Digital TV, and DLP TV, and
Plasma Display Panels.
Using a true 10-bit color depth system, the 30-bit RGB color
produces over 1.07 billion colors to represent High Definition
(HD) displays in their most natural color, surpassing the
maximum 16.7 million colors achieved by 6/8-bit color con-
ventionally used for large-scale LCD televisions and LCD
monitors.
LVDS TRANSMITTER
The LVDS Transmitter serializes LVCMOS/LVTTL RGB
video data and control signal timing into LVDS data streams.
SINGLE PIXEL AND DUAL PIXEL INTERFACE
The DS90C3201 LVDS ports support two modes: Single
Pixel mode (30-bit LVDS output) and Dual Pixel mode (2 x
30-bit LVDS output). For Single Pixel mode, LVDS ports
DOX[A-E] for 10-bit RGB data are utilized. For the Dual Pixel
mode, both DOX[A-E] and DOY[A-E] LVDS ports for odd and
even 10-bit RGB data are utilized.
SELECTABLE INPUT DATA STROBE
The Transmitter input data edge strobe can be latched on
the rising or falling edges of input clock signal. The dedicated
RFB pin is used to program input strobe select on the rising
edge of TXCLK or the falling edge of TXCLK.
2-WIRE SERIAL COMMUNICATION INTERFACE
Optional I2C programming allows fine tuning in development
and production environments. The I2C interface provides
several capabilities to reduce EMI and to customize output
timing. These capabilities are selectable/programmable via
I2C: Programmable LVDS Swing Control, Adjustable Input
Setup/Hold Control, Input/Output Channel Control.
PROGRAMMABLE LVDS SWING CONTROL
Programmable LVDS amplitude (VOD) and LVDS offset volt-
age (VOS) of the differential signals can be adjusted for
better impedance matching for noise and EMI reduction. The
low level LVDS swing mode and offset voltage can be con-
trolled via I2C.
ADJUSTABLE INPUT SETUP/HOLD CONTROL
Programmable LVCMOS/LVTTL Data Input Setup and Hold
Times can be adjusted with respect to TXCLK for convenient
interface with a variety of graphic controllers and video pro-
cessors. Feature is controlled via I2C.
INPUT/OUTPUT CHANNEL CONTROL
Full independent control for input/output channels can be
disabled to minimize power supply line noise and overall
power dissipation. Feature is configured via I2C.
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