ADC121S101_06 Datasheet, PDF (2/17 Pages) National Semiconductor (TI) – Single Channel, 0.5 to Msps, 12-Bit A/D Converter

Block Diagram
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Pin Descriptions and Equivalent Circuits
Pin No.
ANALOG I/O
3
DIGITAL I/O
4
Symbol
V_IN
SCLK
5
SDATA
6
CS
POWER SUPPLY
1
2
PAD
V_A
GND
GND
Description
Analog input. This signal can range from 0V to V_A.
Digital clock input. This clock directly controls the conversion and readout processes.
Digital data output. The output samples are clocked out of this pin on falling edges of
the SCLK pin.
Chip select. On the falling edge of CS, a conversion process begins.
Positive supply pin. This pin should be connected to a quiet +2.7V to +5.25V source
and bypassed to GND with a 1 µF capacitor and a 0.1 µF monolithic capacitor located
within 1 cm of the power pin.
The ground return for the supply and signals.
For package suffix CISD(X) only, it is recommended that the center pad should be
connected to ground.
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