54F378DM Datasheet, PDF (2/8 Pages) National Semiconductor (TI) – Parallel D Register with Enable

Unit Loading Fan Out
54F 74F
Pin Names
Description
UL
Input I_IH I_IL
HIGH LOW Output I_OH I_OL
E
D₀ – D₅
CP
Q₀ – Q₅
Enable Input (Active LOW)
Data Inputs
Clock Pulse Input (Active Rising Edge)
Outputs
10 10
10 10
10 10
50 33 3
20 mA b0 6 mA
20 mA b0 6 mA
20 mA b0 6 mA
b1 mA 20 mA
Functional Description
The ’F378 consists of six edge-triggered D-type flip-flops
with individual D inputs and Q inputs The Clock (CP) and
Enable (E) inputs are common to all flip-flops
When the E input is LOW new data is entered into the
register on the LOW-to-HIGH transition of the CP input
When the E input is HIGH the register will retain the present
data independent of the CP input
Logic Diagram
Truth Table
Inputs
E
CP
D_n
H
L
X
L
L
H
L
L
L
H e HIGH Voltage Level
L e LOW Voltage Level
X e Immaterial
L e LOW-to-HIGH Clock Transition
Output
Q_n
No Change
H
L
TL F 9526 – 5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays
2