54F251ADM Datasheet, PDF (2/8 Pages) National Semiconductor (TI) – 8-Input Multiplexer with TRI-STATE Outputs

Unit Loading Fan Out
Pin Names
S₀ – S₂
OE
I₀ – I₇
Z
Z
Description
Select Inputs
TRI-STATE Output Enable Input (Active LOW)
Multiplexer Inputs
TRI-STATE Multiplexer Output
Complementary TRI-STATE Multiplexer Output
54F 74F
UL
HIGH LOW
10 10
10 10
10 10
150 40 (33 3)
150 40 (33 3)
Input I_IH I_IL
Output I_OH I_OL
20 mA b0 6 mA
20 mA b0 6 mA
20 mA b0 6 mA
b3 mA 24 mA (20 mA)
b3 mA 24 mA (20 mA)
Functional Description
Truth Table
This device is a logical implementation of a single-pole 8-
position switch with the switch position controlled by the
Inputs
state of three Select inputs S₀ S₁ S₂ Both assertion and
negation outputs are provided The Output Enable input
(OE) is active LOW When it is activated the logic function
provided at the output is
Z e OE(I₀S₀S₁ S₂ a I₁S₀S₁S₂ a
I₂S₀S₁S₂ a I₃S₀S₁S₂ a
I₄S₀S₁S₂ a I₅S₀S₁S₂ a
I₆S₀S₁S₂ a I₇S₀S₁S₂)
When the Output Enable is HIGH both outputs are in the
high impedance (High Z) state This feature allows multi-
plexer expansion by tying the outputs of up to 128 devices
together When the outputs of the TRI-STATE devices are
OE
S₂
S₁
S₀
H
X
X
X
L
L
L
L
L
L
L
H
L
L
H
L
L
L
H
H
L
H
L
L
L
H
L
H
L
H
H
L
L
H
H
H
tied together all but one device must be in the high imped-
H e HIGH Voltage Level
ance state to avoid high currents that would exceed the
maximum ratings The Output Enable signals should be de-
signed to ensure there is no overlap in the active LOW por-
L e LOW Voltage Level
X e Immaterial
Z e High Impedance
tion of the enable voltages
Logic Diagram
Outputs
Z
Z
Z
Z
I₀
I₀
I₁
I₁
I₂
I₂
I₃
I₃
I₄
I₄
I₅
I₅
I₆
I₆
I₇
I₇
TL F 9504 – 4
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays
2