54F157ADM Datasheet, PDF (2/8 Pages) National Semiconductor (TI) – Quad 2-Input Multiplexer

Unit Loading Fan Out
Pin Names
Description
I_0a – I_0d
I_1a – I_1d
E
S
Z_a – Z_d
Source 0 Data Inputs
Source 1 Data Inputs
Enable Input (Active LOW)
Select Input
Outputs
54F 74F
UL
HIGH LOW
10 10
10 10
10 10
10 10
50 33 3
Input I_IH I_IL
Output I_OH I_OL
20 mA b0 6 mA
20 mA b0 6 mA
20 mA b0 6 mA
20 mA b0 6 mA
b1 mA 20 mA
Functional Description
The ’F157A is a quad 2-input multiplexer It selects four bits
of data from two sources under the control of a common
Select input (S) The Enable input (E) is active LOW When
E is HIGH all of the outputs (Z) are forced LOW regardless
of all other inputs The ’F157A is the logic implementation of
a 4-pole 2-position switch where the position of the switch
is determined by the logic levels supplied to the Select in-
put The logic equations for the outputs are shown below
Z_n e E  (I_1n S a I_0n S)
A common use of the ’F157A is the moving of data from two
groups of registers to four common output busses The par-
ticular register from which the data comes is determined by
the state of the Select input A less obvious use is as a
function generator The ’F157A can generate any four of the
Logic Diagram
16 different functions of two variables with one variable
common This is useful for implementing highly irregular
logic
Truth Table
Inputs
E
S
I₀
H
X
X
L
H
X
L
H
X
L
L
L
L
L
H
H e HIGH Voltage Level
L e LOW Voltage Level
X e Immaterial
Output
I₁
Z
X
L
L
L
H
H
X
L
X
H
TL F 9483 – 4
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays
2