54ACT563 Datasheet, PDF (2/6 Pages) National Semiconductor (TI) – Octal Latch with TRI-STATE Outputs

Connection Diagrams
Pin Assignment
for DIP and Flatpak
Pin Assignment
for LCC
DS100331-3
Functional Description
The ’ACT563 contains eight D-type latches with TRI-STATE
complementary outputs. When the Latch Enable (LE) input
is HIGH, data on the D_n inputs enters the latches. In this con-
dition the latches are transparent, i.e., a latch output will
change state each time its D input changes. When LE is
LOW the latches store the information that was present on
the D inputs a setup time preceding the HIGH-to-LOW tran-
sition of LE. The TRI-STATE buffers are controlled by the
Output Enable (OE) input. When OE is LOW, the buffers are
in the bi-state mode. When OE is HIGH the buffers are in the
high impedance mode but that does not interfere with enter-
ing new data into the latches.
Logic Diagram
DS100331-4
Function Table
Inputs
Internal
OE LE D
Q
H XX
X
H HL
H
H HH
L
H LX
NC
L HL
H
L HH
L
L LX
NC
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
NC = No Change
Outputs
O
Z
Z
Z
Z
H
L
NC
Function
High-Z
High-Z
High-Z
Latched
Transparent
Transparent
Latched
DS100331-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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