LMX2487 Datasheet, PDF (19/37 Pages) National Semiconductor (TI) – 3.0 GHz - 6.0 GHz High Performance Delta-Sigma Low Power Dual PLLatinum™ Frequency Synthesizers with 3.0 GHz Integer PLL

Bench Test Setups (Continued)
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Input Impedance Measurement Procedure
The above block diagram shows the test setup used for measuring the input impedance for the LMX2487. The DC blocking
capacitor used between the input SMA connector and the pin being measured must be changed to a zero Ohm resistor. This
procedure applies to the FinRF, FinIF, and OSCin pins. The basic test procedure is to calibrate the network analyzer, ensure that
the part is powered up, and then measure the input impedance. The network analyzer can be calibrated by using either calibration
standards or by soldering resistors directly to the evaluation board. An open can be implemented by putting no resistor, a short
can be implemented by soldering a zero ohm resistor as close as possible to the pin being measured, and a short can be
implemented by soldering two 100 ohm resistors in parallel as close as possible to the pin being measured. Calibration is done
with the PLL removed from the PCB. This requires the use of a clamp down fixture that may not always be generally available.
If no clamp down fixture is available, then this procedure can be done by calibrating up to the point where the DC blocking
capacitor usually is, and then implementing port extensions with the network analyzer. Zero ohm resistor is added back for the
actual measurement. Once the setup is calibrated, it is necessary to ensure that the PLL is powered up. This can be done by
toggling the power down bits (RF_PD and IF_PD) and observing that the current consumption indeed increases when the bit is
disabled. Sometimes it may be necessary to apply a signal to the OSCin pin in order to program the part. If this is necessary,
disconnect the signal once it is established that the part is powered up. It is useful to know the input impedance of the PLL for
the purposes of debugging RF problems and designing matching networks. Another use of knowing this parameter is make the
trace width on the PCB such that the input impedance of this trace matches the real part of the input impedance of the PLL
frequency of operation. In general, it is good practice to keep trace lengths short and make designs that are relatively resistant
to variations in the input impedance of the PLL.
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