LMC7101_09 Datasheet, PDF (19/24 Pages) National Semiconductor (TI) – Tiny Low Power Operational Amplifier with Rail-to-Rail Input and Output

4.0 CAPACITIVE LOAD TOLERANCE
The LMC7101 can typically directly drive a 100 pF load with
V_S = 15V at unity gain without oscillating. The unity gain fol-
lower is the most sensitive configuration. Direct capacitive
loading reduces the phase margin of op amps. The combina-
tion of the op amp's output impedance and the capacitive load
induces phase lag. This results in either an underdamped
pulse response or oscillation.
Capacitive load compensation can be accomplished using
resistive isolation as shown in Figure 4. This simple technique
is useful for isolating the capacitive input of multiplexers and
A/D converters.
or
R₁ C_IN ≤ R₂ C_f
which typically provides significant overcompensation.
Printed circuit board stray capacitance may be larger or small-
er than that of a breadboard, so the actual optimum value for
C_F may be different. The values of C_F should be checked on
the actual circuit. (Refer to the LMC660 quad CMOS amplifier
data sheet for a more detailed discussion.)
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FIGURE 4. Resistive Isolation
of a 330 pF Capacitive Load
5.0 COMPENSATING FOR INPUT CAPACITANCE WHEN
USING LARGE VALUE FEEDBACK RESISTORS
When using very large value feedback resistors, (usually
> 500 kΩ) the large feed back resistance can react with the
input capacitance due to transducers, photodiodes, and cir-
cuit board parasitics to reduce phase margins.
The effect of input capacitance can be compensated for by
adding a feedback capacitor. The feedback capacitor (as in
Figure 5), C_f is first estimated by:
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FIGURE 5. Cancelling the Effect of Input Capacitance
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