LM4931_06 Datasheet, PDF (19/48 Pages) National Semiconductor (TI) – Audio Subsystem with Mono High Efficiency Loudsperker and Stereo Headphone Amplifiers

PLL Configuration Registers
This register is used to control the frequency divider (M divider) which sits before the PLL phase comparator, it also allows the
3 MSBs of the N_divider’s modulus input to be programmed. See Figure 4 for further explanation.
DEFAULT CHART FOR PLL_M (05h)
DATA BIT
7
6
5
4
3
2
1
0
DEFAULT
0
0
0
0
0
0
0
0
Address
4:0
7:5
PLL_M (05h) (SET = LOGIC 1, CLEAR = LOGIC 0)
Register
PLL_M
PLL_N_MOD1
Description
Programs the PLL input divider from divide by 4 to divide by 31. It is also
possible to bypass the divider if PLL_M = 1 or divide by 2 if PLL_M = 2. Setting
PLL_M = 3 will default to divide by 4.
Programs the modulus bits [4:2] of the PLL feedback divider .
This register is used to control the integer of the PLL feedback divider (fractional N divider).
DEFAULT CHART FOR PLL_N (06h)
DATA BIT
7
6
5
4
3
2
1
0
DEFAULT
0
0
0
0
0
0
0
0
Address
6:0
7
Register
PLL_N
FAST_VCO
PLL_N (06n) (SET = LOGIC 1, CLEAR = LOGIC 0)
Description
Programs the PLL feedback divider from divide by 4 to divide by 127, PLL_N
inputs from 0 to 3 are rounded to 4.
If set the VCO operates best at frequencies up to 100MHz, normally the VCO is
tuned for outputs around 50MHz.
This register is used to control the PLL output divider (P divider), it also allows the 2 LSBs of the N divider’s modulus input to be
programmed.
DATA BIT
7
DEFAULT
0
DEFAULT CHART FOR PLL_P (07h)
6
5
4
3
2
0
0
0
0
0
1
0
0
0
Address
3:0
5:4
7:6
PLL_P (07h) (SET = LOGIC 1, CLEAR = LOGIC 0)
Register
PLL_P
PLL_N_MOD2
DITHER_LEVEL
Description
Programs the PLL output divider from divide by 4 to divide by 15, PLL_P inputs
from 0 to 3 are rounded to 4. It is recommended that P = 4 to keep the VCO
around its nominal frequency of 50MHz.
Programs the PLL feedback divider modulus bits [1:0].
Programs the magnitude of the PLL dither level.
7:6
PLL Dither Level
00
32
01
16
10
48
11
0
The N divider is a fractional divider as such:
N = PLL_N + (PLL _NMOD/32)
If the Modulus input is zero then the N divider is simpler an integer N divider. The output from the PLL is determined by the
following formula:
Fout = (Fin*N)/(PLL_M*PLL_P)
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