ADC16061_06 Datasheet, PDF (19/21 Pages) National Semiconductor (TI) – Self-Calibrating 16-Bit, 2.5MSPS, 390mW A/D Converter

Applications Information (Continued)
FIGURE 9. Example at a suitable layout.
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6.0 DYNAMIC PERFORMANCE
To achieve the best dynamic performance with the
ADC16061, the clock source driving the CLK input must be
free of jitter. For best a.c. performance, isolate the ADC clock
from any digital circuitry with buffers, as with the clock tree
shown in Figure 10.
As mentioned in section 5.0, it is good practice to keep the
ADC clock line as short as possible and to keep it well away
from any other signals. Other signals can introduce phase
noise (jitter) into the clock signal, which can lead to in-
creased distortion. Even lines with 90˚ crossings have ca-
pacitive coupling, so try to avoid even these 90˚ crossings of
the clock line.
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FIGURE 10. Isolating the ADC clock from other
circuitry with a clock tree.
7.0 COMMON APPLICATION PITFALLS
Driving the inputs (analog or digital) beyond the power
supply rails. For proper operation, all inputs should not go
more than 100 mV beyond the supply rails (more than 100
mV below the ground pins or 100 mV above the supply pins).
Exceeding these limits on even a transient basis may cause
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