ADC12C105 Datasheet, PDF (19/24 Pages) National Semiconductor (TI) – 12-Bit, 95/105 MSPS A/D Converter

TABLE 1. Input to Output Relationship
V_IN+
V_CM − V_REF/2
V_CM − V_REF/4
V_CM
V_CM + V_REF/4
V_CM + V_REF/2
V_IN−
V_CM + V_REF/2
V_CM + V_REF/4
V_CM
V_CM − V_REF/4
V_CM − V_REF/2
Binary Output
0000 0000 0000
0100 0000 0000
1000 0000 0000
1100 0000 0000
1111 1111 1111
2’s Complement Output
1000 0000 0000
1100 0000 0000
0000 0000 0000
0100 0000 0000
0111 1111 1111
Negative Full-Scale
Mid-Scale
Positive Full-Scale
2.1.2 Driving the Analog Inputs
The V_IN+ and the V_IN− inputs of the ADC12C105 have an in-
ternal sample-and-hold circuit which consists of an analog
switch followed by a switched-capacitor amplifier.
Figure 5 and Figure 5 show examples of single-ended to dif-
ferential conversion circuits. The circuit in Figure 5 works well
for input frequencies up to approximately 70MHz, while the
circuit in Figure 6 works well above 70MHz.
30023120
FIGURE 5. Low Input Frequency Transformer Drive Circuit
30023121
FIGURE 6. High Input Frequency Transformer Drive Circuit
One short-coming of using a transformer to achieve the sin-
gle-ended to differential conversion is that most RF trans-
formers have poor low frequency performance. A differential
amplifier can be used to drive the analog inputs for low fre-
quency applications. The amplifier must be fast enough to
settle from the charging glitches on the analog input resulting
from the sample-and-hold operation before the clock goes
high and the sample is passed to the ADC core.
The SFDR performance of the converter depends on the ex-
ternal signal conditioning circuity used, as this affects how
quickly the sample-and-hold charging glitch will settle. An ex-
ternal resistor and capacitor network as shown in Figure 7
should be used to isolate the charging glitches at the ADC
input from the external driving circuit and to filter the wideband
noise at the converter input. These components should be
placed close to the ADC inputs because the analog input of
the ADC is the most sensitive part of the system, and this is
the last opportunity to filter that input. For Nyquist applications
the RC pole should be at the ADC sample rate. The ADC input
capacitance in the sample mode should be considered when
setting the RC pole. For wideband undersampling applica-
tions, the RC pole should be set at least 1.5 to 2 times the
maximum input frequency to maintain a linear delay re-
sponse.
2.1.3 Input Common Mode Voltage
The input common mode voltage, V_CM, should be in the range
of 1.4V to 1.6V and be a value such that the peak excursions
of the analog signal do not go more negative than ground or
more positive than 2.6V. It is recommended to use V_CMO (pin
32) as the input common mode voltage.
If the ADC12C105 is operated with V_A=3.6V, a resistor of ap-
proximately 1KΩ should be used from the V_CMO pin to
AGND.This will help maintain stability over the entire temper-
ature range when using a high supply voltage.
2.2 Reference Pins
The ADC12C105 is designed to operate with an internal or
external 1.2V reference. The internal 1.2 Volt reference is the
default condition when no external reference input is applied
to the V_REF pin. If a voltage is applied to the V_REF pin, then
that voltage is used for the reference. The V_REF pin should
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