PC87322VF Datasheet, PDF (18/84 Pages) National Semiconductor (TI) – Floppy Disk Controller with Dual UARTs, Enhanced Parallel Port, and IDE Interface

2 0 Configuration Registers (Continued)
2 5 4 Function Control Register (FCR Index e 3)
This register determines several pin options
It selects between Data Rate output and automatic media
sense inputs and between IDENT or IDEACK inputs for
DMA control of IDE
It enables the Parallel Port Multiplexor (PPM) and switches
between internal and external drives
For Enhanced Parallel Port it enables the IOCHRDY and
ZWS options and pins
On reset the FCR 1 7 bits are cleared to zero
Bit 0 Media Sense Data Rate select bit When this bit is 0
the MSEN0 –1 pins are Media Sense inputs When
this bit is 1 the DRATE0–1 pins are Data Rate out-
puts VLD0 pin is sampled during reset to this bit
Bit 1 IDENT IDEACK select bit When this bit is zero the
IDENT pin is used and the IDE DMA is disabled
When this bit is 1 the IDE DMA is enabled and the
IDENT input is assumed to be 1
Bit 2 Printer Floppy Parallel Port Multiplexor (PPM) enable
bit When this bit is 0 the PPM is disabled and the
parallel port pins are configured When this bit is 1
the PPM is enabled See PNF pin description for fur-
ther information The DRV2 PNF pin is read as DRV2
bit regardless of bit 2 of FCR
Bit 3 Parallel Port Multiplexor (PPM) float control bit When
this bit is 0 the PPM pins are driven When this bit is
1 the PPM pins are in TRI-STATE mode and the pull-
ups are disconnected
Bit 4 Logical Drive Exchange bit This bit allows software to
exchange the physical floppy-disk control signals as-
signed to drives 0 and 1 thus exchanging the logical
drives A and B
This is accomplished by exchanging control of the
DR0 and MTR0 pins with the DR1 and MTR1 pins
Undefined result if this bit is set while bit 4 of FER is 1
Table 2-9 shows the associations between the Con-
figuration Register bit the Digital Output Register bits
(DRVSEL0 1 and MTR0 1) and the drive and motor
control pins (DR0 1 and MTR0 1)
TABLE 2-9 Logical Drive Exchange
FCR
Digital Output Register (FDC)
Asserted
Bit 4 MTR1 MTR0 DRVSEL1 DRVSEL0 ^{FDC Pins}
0
0
1
0
0
DR0
MTR0
0
1
0
0
1
DR1
MTR1
1
0
1
0
0
DR1
MTR1
1
1
0
0
1
DR0
MTR0
Bit 5 Zero Wait State enable bit If this bit is 1 (and pin 3 is
configured as ZWS) ZWS is driven low when the En-
hanced Parallel Port (EPP) or an ECP can accept a
short host read write-cycle otherwise the ZWS open
drain output is not driven EPP ZWS write operation
should be configured when the system’s device is fast
enough to support it
Bit 6 ZWS CSOUT PWDN select bit When this bit is 0 the
ZWS pin is Zero Wait State output When this bit is 1
the PWDN CSOUT pin option is selected (See bit 2
of PTR register )
Bit 7 IOCHRDY MFM select bit When this bit is 0 the
IOCHRDY pin is IOCHRDY open drain output that ex-
tends the host-EPP cycle when required When this
bit is 1 the MFM pin is selected
2 5 5 Printer Control Register (PCR Index e 4)
This register enables the EPP and version modes On reset
the PCR 0 1 bits are cleared to zero
Bit 0 EPP enable bit When this bit is 0 the EPP is disabled
and the EPP registers are not accessible (access ig-
nored) When this bit is 1 the EPP is enabled Note
that the EPP should not be configured with base ad-
dress 3BCh
Bit 1 EPP version select bit When this bit is zero Version
1 7 is supported When this bit is 1 Version 1 9 is sup-
ported (IEEE 1284)
Bits 2 3 Reserved
Bit 4 EPP interrupt control bit When this bit is 0 the EPP
generates a pulse interrupt When this bit is 1 the EPP
generates a level interrupt
Bits 5 6 and 7 Reserved
2 6 POWER-DOWN OPTIONS
There are various methods for entering the power-down
mode All methods result in one of three possible modes
This section associates the methods of entering the power-
down with the resulting mode
Mode 1 The internal clock stops for a specific function (i e
UART1 and or UART2 and or FDC)
This mode is entered by any of the following
1 Clear the FER bit for the specific function that is powered
down See Section 2 5 1 FER bits 1 – 3
2 During reset set certain CFG0 – 4 pins See Table 2-1
3 Execute the FDC Mode Command with PTR bit 1 e 0
(XTAL CLK) See Section 4 2 6 LOW PWR
4 Set Data Rate Select Register bit 6 in the FDC high with
PTR bit 1 e 0 See Section 3 6 bit 6
Mode 2 The internal clocks are stopped for all enabled
functions
Note Clocks to disabled functions are always inactive
This mode is entered by any of the following
1 Clear all FER bits for any enabled function See Section
2 5 1 FER bits 1 – 3
2 Clear PTR bits 1 (XTAL CLK) and 2 (CSOUT PWDN se-
lect) and set bit 6 of FCR Then assert the PWDN signal
low See Section 2 5 3 PTR bits 1 2 and Section 1 0
PWDN pin
3 Clear PTR bit 1 and then set PTR bit 0 (Power-Down)
high See Section 2 5 3 PTR bits 0 and 1
Mode 3 The external crystal is stopped and internal clocks
are stopped for all enabled functions
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