LMH6321_07 Datasheet, PDF (18/22 Pages) National Semiconductor (TI) – 300mA High Speed Buffer with Adjustable Current Limit

20138630
FIGURE 4. Thermal Resistance (typ) for 7-L TO-263
Package Mounted on 1 oz. (0.036 mm) PC Board Foil
20138631
FIGURE 5. Derating Curve for TO-263 package.
No Air Flow
TABLE 1. θ_JA vs. Copper Area and P_D for TO-263. 1.0 oz
cu Board. No Air Flow. Ambient Temperature = 24°C
Copper Area
θJA @ 1.0W
(°C/W)
θJA @ 2.0W
(°C/W)
1 Layer = 1”x2” cu
62.4
54.7
Bottom
2 Layer = 1”x2” cu
36.4
32.1
Top & Bottom
2 Layer = 2”x2” cu
23.5
22.0
Top & Bottom
2 Layer = 2”x4” cu
19.8
17.2
Top & Bottom
As seen in the previous example, buffer dissipation in DC cir-
cuit applications is easily computed. However, in AC circuits,
signal wave shapes and the nature of the load (reactive, non-
reactive) determine dissipation. Peak dissipation can be sev-
eral times the average with reactive loads. It is particularly
important to determine dissipation when driving large load
capacitance.
A selection of thermal data for the PSOP package is shown
in Table 2. The table summarized θ_JA for both 0.5 watts and
0.75 watts. Note that the thermal resistance, for both the
TO-263 and the PSOP package is lower for the higher power
dissipation levels. This phenomenon is a result of the principle
of Newtons Law of Cooling. Restated in term of heatsink cool-
ing, this principle says that the rate of cooling and hence the
thermal conduction, is proportional to the temperature differ-
ence between the junction and the outside environment (am-
bient). This difference increases with increasing power levels,
thereby producing higher die temperatures with more rapid
cooling.
TABLE 2. θ_JA vs. Copper Area and P_D for PSOP. 1.0 oz cu
Board. No Airflow. Ambient Temperature = 22°C
Copper Area/Vias
θJA @ 0.5W
(°C/W)
θJA @ 0.75W
(°C/W)
1 Layer = 0.05 sq. in.
(Bottom) + 3 Via Pads
141.4
138.2
1 Layer = 0.1 sq. in.
(Bottom) + 3 Via Pads
134.4
131.2
1 Layer = 0.25 sq. in.
(Bottom) + 3 Via Pads
115.4
113.9
1 Layer = 0.5 sq. in.
(Bottom) + 3 Via Pads
105.4
104.7
1 Layer = 1.0 sq. in.
(Bottom) + 3 Via Pads
100.5
100.2
2 Layer = 0.5 sq. in.
93.7
92.5
(Top)/ 0.5 sq. in.
(Bottom) + 33 Via Pads
2 Layer = 1.0 sq. in.
82.7
82.2
(Top)/ 1.0 sq. in.
(Bottom) + 53 Via Pads
ERROR FLAG OPERATION
The LMH6321 provides an open collector output at the EF pin
that produces a low voltage when the Thermal Shutdown
Protection is engaged, due to a fault condition. Under normal
operation, the Error Flag pin is pulled up to V⁺ by an external
resistor. When a fault occurs, the EF pin drops to a low voltage
and then returns to V⁺ when the fault disappears. This voltage
change can be used as a diagnostic signal to alert a micro-
processor of a system fault condition. If the function is not
used, the EF pin can be either tied to ground or left open. If
this function is used, a 10 kΩ, or larger, pull-up resistor (R₂ in
Figure 2) is recommended. The larger the resistor the lower
the voltage will be at this pin under thermal shutdown. Table
3 shows some typical values of V_EF for 10 kΩ and 100 kΩ.
TABLE 3. V_EF vs. R₂ Figure 2
R₂
@ V⁺ = 5V
@V⁺ = 15V
10 kΩ
0.24V
0.55V
100 KΩ
0.036V
0.072V
www.national.com
18