COP87L88GD Datasheet, PDF (18/39 Pages) National Semiconductor (TI) – 8-Bit CMOS OTP Microcontrollers with 16k or 32k Memory and 8-Channel A/D with Prescaler

A/D Converter (Continued)
CHANNEL SELECT
This 3-bit field selects one of eight channels to be the V_IN+.
The mode selection determines the V_IN− input.
Single Ended mode:
Bit 7
Bit 6
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
Differential mode:
Bit 5
0
1
0
1
0
1
0
1
Channel No.
0
1
2
3
4
5
6
7
Bit 7
Bit 6
Bit 5
Channel Pairs (+, −)
0
0
0
0, 1
0
0
1
1, 0
0
1
0
2, 3
0
1
1
3, 2
1
0
0
4, 5
1
0
1
5, 4
1
1
0
6, 7
1
1
1
7, 6
MODE SELECT
This 2-bit field is used to select the mode of operation (single
conversion, continuous conversions, differential, single
ended) as shown in the following table.
Bit 4 Bit 3
Mode
0
0 Single Ended mode, single
conversion
0
1 Single Ended mode, continuous scan
of a single channel into the result
register
1
0 Differential mode, single conversion
1
1 Differential mode, continuous scan of
a channel pair into the result register
PRESCALER SELECT
This 2-bit field is used to select one of the four prescaler
clocks for the A/D converter. The following table shows the
various prescaler options.
A/D Converter Clock Prescale
Bit 2
0
0
1
1
Bit 1
0
1
0
1
Clock Select
Divide by 2
Divide by 4
Divide by 6
Divide by 12
BUSY BIT
The ADBSY bit of the ENAD register is used to control start-
ing and stopping of the A/D conversion. When ADBSY is
cleared, the prescale logic is disabled and the A/D clock is
turned off. Setting the ADBSY bit starts the A/D clock and ini-
tiates a conversion based on the mode select value currently
in the ENAD register. Normal completion of an A/D conver-
sion clears the ADBSY bit and turns off the A/D converter.
The ADBSY bit remains a one during continuous conversion.
The user can stop continuous conversion by writing a zero to
the ADBSY bit.
If the user wishes to restart a conversion which is already in
progress, this can be accomplished only by writing a zero to
the ADBSY bit to stop the current conversion and then by
writing a one to ADBSY to start a new conversion. This can
be done in two consecutive instructions.
ADC Operation
The A/D converter interface works as follows. Setting the
ADBSY bit in the A/D control register ENAD initiates an A/D
conversion. The conversion sequence starts at the begin-
ning of the write to ENAD operation which sets ADBSY, thus
powering up the A/D. At the first falling edge of the converter
clock following the write operation, the sample signal turns
on for seven clock cycles. If the A/D is in single conversion
mode, the conversion complete signal from the A/D will gen-
erate a power down for the A/D converter and will clear the
ADBSY bit in the ENAD register at the next instruction cycle
boundary. If the A/D is in continuous mode, the conversion
complete signal will restart the conversion sequence by de-
selecting the A/D for one converter clock cycle before start-
ing the next sample. The A/D 8-bit result is immediately
loaded into the A/D result register (ADRSLT) upon comple-
tion. Internal logic prevents transient data (resulting from the
A/D writing a new result over an old one) being read from
ADRSLT.
Inadvertent changes to the ENAD register during conversion
are prevented by the control logic of the A/D. Any attempt to
write any bit of the ENAD Register except ADBSY, while
ADBSY is a one, is ignored. ADBSY must be cleared either
by completion of an A/D conversion or by the user before the
prescaler, conversion mode or channel select values can be
changed. After stopping the current conversion, the user can
load different values for the prescaler, conversion mode or
channel select and start a new conversion in one instruction.
It is important for the user to realize that, when used in differ-
ential mode, only the positive input to the A/D converter is
sampled and held. The negative input is constantly con-
nected and should be held stable for the duration of the con-
version. Failure to maintain a stable negative input will result
in incorrect conversion.
PRESCALER
The A/D Converter (A/D) contains a prescaler option that al-
lows four different clock selections. The A/D clock frequency
is equal to CKI divided by the prescaler value. Note that the
prescaler value must be chosen such that the A/D clock falls
within the specified range. The maximum A/D frequency is
1.67 MHz. This equates to a 600 ns A/D clock cycle.
www.national.com
18