THS4042 Datasheet, PDF (17/34 Pages) National Semiconductor (TI) – 165-MHz C-STABLE HIGH-SPEED AMPLIFIER

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THS4041, THS4042
165ĆMHz CĆSTABLE HIGHĆSPEED AMPLIFIERS
SLOS237B− MAY 1999 − REVISED FEBRUARY 2000
APPLICATION INFORMATION
offset voltage
The output offset voltage, (V_OO) is the sum of the input offset voltage (V_IO) and both input bias currents (I_IB) times
the corresponding gains. The following schematic and formula can be used to calculate the output offset
voltage:
RF
IIB−
RG
+
−
VI
+
VO
RS
IIB+
ǒ ǒ ǓǓ ǒ ǒ ǓǓ VOO + VIO
1)
RF
RG
" IIB₎ RS
1)
RF
RG
" IIB– RF
Figure 67. Output Offset Voltage Model
optimizing unity gain response
Internal frequency compensation of the THS404x was selected to provide very wideband performance yet still
maintain stability when operated in a noninverting unity gain configuration. When amplifiers are compensated
in this manner there is usually peaking in the closed loop response and some ringing in the step response for
very fast input edges, depending upon the application. This is because a minimum phase margin is maintained
for the G=+1 configuration. For optimum settling time and minimum ringing, a feedback resistor of 200 Ω should
be used as shown in Figure 68. Additional capacitance can also be used in parallel with the feedback resistance
if even finer optimization is required.
Input
+
THS404x
_
Output
200 Ω
Figure 68. Noninverting, Unity Gain Schematic
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