LMZ14203H_1106 Datasheet, PDF (17/20 Pages) National Semiconductor (TI) – 3A SIMPLE SWITCHER® Power Module for High Output Voltage

Package Thermal Resistance θ_JA 4 Layer Printed Circuit
Board with 1oz Copper
40
0LFM (0m/s) air
35
225LFM (1.14m/s) air
500LFM (2.54m/s) air
Evaluation Board Area
30
25
20
15
10
5
0
0 10 20 30 40 50 60
BOARD AREA (cm2)
30135689
For θ_JA-MAX< 17.1°C/W and only natural convection (i.e. no air
flow), the PCB area will have to be at least 52cm². This cor-
responds to a square board with 7.25cm x 7.25cm (2.85in x
2.85in) copper area, 4 layers, and 1oz copper thickness.
Higher copper thickness will further improve the overall ther-
mal performance. As a reference, the evaluation board has
2oz copper on the top and bottom layers, achieving θ_JA of
14.9°C/W for the same board area. Note that thermal vias
should be placed under the IC package to easily transfer heat
from the top layer of the PCB to the inner layers and the bot-
tom layer.
For more guidelines and insight on PCB copper area, thermal
vias placement, and general thermal design practices please
refer to Application Note AN-2020 (http://www.national.com/
an/AN/AN-2020.pdf).
PC BOARD LAYOUT GUIDELINES
PC board layout is an important part of DC-DC converter de-
sign. Poor board layout can disrupt the performance of a DC-
DC converter and surrounding circuitry by contributing to EMI,
ground bounce and resistive voltage drop in the traces. These
can send erroneous signals to the DC-DC converter resulting
in poor regulation or instability. Good layout can be imple-
mented by following a few simple design rules.
1. Minimize area of switched current loops.
30135611
From an EMI reduction standpoint, it is imperative to minimize
the high di/dt paths during PC board layout. The high current
loops that do not overlap have high di/dt content that will
cause observable high frequency noise on the output pin if
the input capacitor (Cin1) is placed at a distance away from
the LMZ14203H. Therefore place C_IN1 as close as possible to
the LMZ14203H VIN and GND exposed pad. This will mini-
mize the high di/dt area and reduce radiated EMI. Addition-
ally, grounding for both the input and output capacitor should
consist of a localized top side plane that connects to the GND
exposed pad (EP).
2. Have a single point ground.
The ground connections for the feedback, soft-start, and en-
able components should be routed to the GND pin of the
device. This prevents any switched or load currents from
flowing in the analog ground traces. If not properly handled,
poor grounding can result in degraded load regulation or er-
ratic output voltage ripple behavior. Provide the single point
ground connection from pin 4 to EP.
3. Minimize trace length to the FB pin.
Both feedback resistors, R_FBT and R_FBB, and the feed forward
capacitor C_FF, should be located close to the FB pin. Since
the FB node is high impedance, maintain the copper area as
small as possible. The traces from R_FBT, R_FBB, and C_FF should
be routed away from the body of the LMZ14203H to minimize
noise pickup.
4. Make input and output bus connections as wide as
possible.
This reduces any voltage drops on the input or output of the
converter and maximizes efficiency. To optimize voltage ac-
curacy at the load, ensure that a separate feedback voltage
sense trace is made to the load. Doing so will correct for volt-
age drops and provide optimum output accuracy.
5. Provide adequate device heat-sinking.
Use an array of heat-sinking vias to connect the exposed pad
to the ground plane on the bottom PCB layer. If the PCB has
a plurality of copper layers, these thermal vias can also be
employed to make connection to inner layer heat-spreading
ground planes. For best results use a 6 x 6 via array with
minimum via diameter of 10mils (254 μm) thermal vias spaced
59mils (1.5 mm). Ensure enough copper area is used for heat-
sinking to keep the junction temperature below 125°C.
Additional Features
OUTPUT OVER-VOLTAGE COMPARATOR
The voltage at FB is compared to a 0.92V internal reference.
If FB rises above 0.92V the on-time is immediately terminat-
ed. This condition is known as over-voltage protection (OVP).
It can occur if the input voltage is increased very suddenly or
if the output load is decreased very suddenly. Once OVP is
activated, the top MOSFET on-times will be inhibited until the
condition clears. Additionally, the synchronous MOSFET will
remain on until inductor current falls to zero.
CURRENT LIMIT
Current limit detection is carried out during the off-time by
monitoring the current in the synchronous MOSFET. Refer-
ring to the Functional Block Diagram, when the top MOSFET
is turned off, the inductor current flows through the load, the
PGND pin and the internal synchronous MOSFET. If this cur-
rent exceeds 4.2A (typical) the current limit comparator dis-
ables the start of the next on-time period. The next switching
cycle will occur only if the FB input is less than 0.8V and the
inductor current has decreased below 4.2A. Inductor current
is monitored during the period of time the synchronous MOS-
FET is conducting. So long as inductor current exceeds 4.2A,
further on-time intervals for the top MOSFET will not occur.
Switching frequency is lower during current limit due to the
longer off-time. It should also be noted that DC current limit
varies with duty cycle, switching frequency, and temperature.
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