ADC122S625 Datasheet, PDF (17/20 Pages) National Semiconductor (TI) – Dual 12-Bit, 50 kSPS to 200 kSPS, Simultaneous Sampling A/D Converter

5.0 POWER SUPPLY CONSIDERATIONS AND PCB
LAYOUT
For best performance, care should be taken with the physical
layout of the printed circuit board. This is especially true with
a low reference voltage or when the conversion rate is high.
At high clock rates there is less time for settling, so it is im-
portant that any noise settles out before the conversion be-
gins.
5.1 Analog Power Supply
Any ADC architecture is sensitive to spikes on the power sup-
ply, reference, and ground pins. These spikes may originate
from switching power supplies, digital logic, high power de-
vices, and other sources. Power to the ADC122S625 should
be clean and well bypassed. A 0.1 µF ceramic bypass ca-
pacitor and a 1 µF to 10 µF capacitor should be used to
bypass the ADC122S625 supply, with the 0.1 µF capacitor
placed as close to the ADC122S625 package as possible.
Since the ADC122S625 has a separate analog and reference
pin, the user has two options. The first option is to tie the ana-
log and reference supply pins together and power them with
the same power supply. This is the most cost effective way of
powering the ADC122S625 but it is also the least ideal. As
stated previously, noise from the analog supply pin can cou-
ple into the reference supply pin and adversely affect perfor-
mance. The other option involves the user powering the
analog and reference supply pins with separate supply volt-
ages. These supply voltages can have the same amplitude or
they can be different. The only design constraint is that the
reference supply voltage be less than the analog supply volt-
age.
5.2 Voltage Reference
The reference source must have a low output impedance and
needs to be bypassed with a minimum capacitor value of 0.1
µF. A larger capacitor value of 1 µF to 10 µF placed in parallel
with the 0.1 µF is preferred. While the ADC122S625 draws
very little current from the reference on average, there are
higher instantaneous current spikes at the reference input.
The reference input of the ADC122S625, like all A/D convert-
ers, does not reject noise or voltage variations. Keep this in
mind if the reference voltage is derived from the power supply.
Any noise and/or ripple from the supply that is not rejected by
the external reference circuitry will appear in the digital re-
sults. The use of an active reference source is recommended.
The LM4040 and LM4050 shunt reference families and the
LM4132 and LM4140 series reference families are excellent
choices for a reference source.
5.3 PCB Layout
Capacitive coupling between the noisy digital circuitry and the
sensitive analog circuitry can lead to poor performance. The
solution is to keep the analog circuitry separated from the
digital circuitry and the clock line as short as possible. Digital
circuits create substantial supply and ground current tran-
sients. The logic noise generated could have significant im-
pact upon system noise performance. To avoid performance
degradation of the ADC122S625 due to supply noise, avoid
sharing the power supplies for V_A and V_REF with other digital
circuity on the board.
Generally, analog and digital lines should cross each other at
90° to avoid crosstalk. However, to maximize accuracy in high
resolution systems, avoid crossing analog and digital lines al-
together. It is important to keep clock lines as short as possi-
ble and isolated from other lines, including other digital lines.
In addition, the clock line should also be treated as a trans-
mission line and be properly terminated. The analog input
should be isolated from noisy signal traces to avoid coupling
of spurious signals into the input. Any external component
(e.g., a filter capacitor) connected between the converter's
input pins and ground or to the reference input pin and ground
should be connected to a very clean point in the ground plane.
A single, uniform ground plane and the use of split power
planes are recommended. The power planes should be lo-
cated within the same board layer. All analog circuitry (input
amplifiers, filters, reference components, etc.) should be
placed over the analog power plane. All digital circuitry and
I/O lines should be placed over the digital power plane. Fur-
thermore, the GND pin on the ADC122S625 and all the
components in the reference circuitry and input signal chain
that are connected to ground should be connected to the
ground plane at a quiet point. Avoid connecting these points
too close to the ground point of a microprocessor, microcon-
troller, digital signal processor, or other high power digital
device.
6.0 APPLICATION CIRCUITS
The following figures are examples of the ADC122S625 in
typical application circuits. These circuits are basic and will
generally require modification for specific circumstances.
6.1 Data Acquisition
Figure 11 shows a basic low cost, low power data acquisition
circuit. The analog supply pin is powered by the system +5V
supply and the 2.5V reference voltage is generated by the
LM4040-2.5 shunt reference.
30055334
FIGURE 11. Low cost, low power Data Acquisition
System
6.2 Current Sensing Application
Figure 12 shows an example of interfacing a pair of current
transducers to the ADC122S625. The current transducers
convert an input current into a voltage that is converted by the
ADC122S625. Since the output voltage of the current trans-
ducers are single-ended and centered around a common-
mode voltage of 2.5V, the ADC122S625 is configured with the
output of the transducer driving the non-inverting inputs and
the common-mode output voltage of the transducer driving
the inverting input. The output of the transducer has an output
range of ±2V around the common-mode voltage of 2.5V. As
a result, a series reference voltage of 2.0V is connected to the
ADC122S625. This will allow all of the codes of the
ADC122S625 to be available for the application. This config-
uration of the ADC122S625 is referred to as a single-ended
application of a differential ADC. All of the elements in the
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