ADC11C170 Datasheet, PDF (17/22 Pages) National Semiconductor (TI) – 11-Bit, 170 MSPS, 1.1 GHz Bandwidth A/D Converter with CMOS outputs

TABLE 1. Input to Output Relationship
V_IN+
V_CM − V_REF/2
V_CM − V_REF/4
V_CM
V_CM + V_REF/4
V_CM + V_REF/2
V_IN−
V_CM + V_REF/2
V_CM + V_REF/4
V_CM
V_CM − V_REF/4
V_CM − V_REF/2
Binary Output
000 0000 0000
010 0000 0000
100 0000 0000
110 0000 0000
111 1111 1111
2’s Complement Output
100 0000 0000
110 0000 0000
000 0000 0000
010 0000 0000
011 1111 1111
Negative Full-Scale
Mid-Scale
Positive Full-Scale
2.1.2 Driving the Analog Inputs
The V_IN+ and the V_IN− inputs of the ADC11C170 have an in-
ternal sample-and-hold circuit which consists of an analog
switch followed by a switched-capacitor amplifier. The analog
inputs are connected to the sampling capacitors through
NMOS switches, and each analog input has parasitic capac-
itances associated with it.
When the clock is high, the converter is in the sample phase.
The analog inputs are connected to the sampling capacitor
through the NMOS switches, which causes the capacitance
at the analog input pins to appear as the pin capacitance plus
the internal sample and hold circuit capacitance (approxi-
mately 9 pF). While the clock level remains high, the sampling
capacitor will track the changing analog input voltage. When
the clock transitions from high to low, the converter enters the
hold phase, during which the analog inputs are disconnected
from the sampling capacitor. The last voltage that appeared
at the analog input before the clock transition will be held on
the sampling capacitor and will be sent to the ADC core. The
capacitance seen at the analog input during the hold phase
appears as the sum of the pin capacitance and the parasitic
capacitances associated with the sample and hold circuit of
each analog input (approximately 6 pF). Once the clock signal
transitions from low to high, the analog inputs will be recon-
nected to the sampling capacitor to capture the next sample.
Usually, there will be a difference between the held voltage
on the sampling capacitor and the new voltage at the analog
input. This will cause a charging glitch that is proportional to
the voltage difference between the two samples to appear at
the analog input pin. The input circuitry must be fast enough
to allow the sampling capacitor to settle before the clock sig-
nal goes low again, as incomplete settling can degrade the
SFDR performance.
A single-ended to differential conversion circuit is shown in
Figure 4. A transformer is preferred for high frequency input
signals. Terminating the transformer on the secondary side
provides two advantages. First, it presents a real broadband
impedance to the ADC inputs and second, it provides a com-
mon path for the charging glitches from each side of the
differential sample-and-hold circuit.
One short-coming of using a transformer to achieve the sin-
gle-ended to differential conversion is that most RF trans-
formers have poor low frequency performance. A differential
amplifier can be used to drive the analog inputs for low fre-
quency applications. The amplifier must be fast enough to
settle from the charging glitches on the analog input resulting
from the sample-and-hold operation before the clock goes
high and the sample is passed to the ADC core.
The SFDR performance of the converter depends on the ex-
ternal signal conditioning circuity used, as this affects how
quickly the sample-and-hold charging glitch will settle. An ex-
ternal resistor and capacitor network as shown in Figure 4
should be used to isolate the charging glitches at the ADC
input from the external driving circuit and to filter the wideband
noise at the converter input. These components should be
placed close to the ADC inputs because the analog input of
the ADC is the most sensitive part of the system, and this is
the last opportunity to filter that input. For Nyquist applications
the RC pole should be at the ADC sample rate. The ADC input
capacitance in the sample mode should be considered when
setting the RC pole. For wideband undersampling applica-
tions, the RC pole should be set at about 1.5 to 2 times the
maximum input frequency to maintain a linear delay re-
sponse.
2.1.3 Input Common Mode Voltage
The input common mode voltage, V_CM, should be in the range
of 1.4V to 1.6V and be a value such that the peak excursions
of the analog signal do not go more negative than ground or
more positive than 2.6V. It is recommended to use V_RM (pin
45) as the input common mode voltage.
2.2 Reference Pins
The ADC11C170 is designed to operate with an internal 1.0V
reference, or an external 1.0V reference, but performs well
with external reference voltages in the range of 0.9V to 1.1V.
The internal 1.0 Volt reference is the default condition when
no external reference input is applied to the V_REF pin. If a volt-
age in the range of 0.9V to 1.1V is applied to the V_REF pin,
then that voltage is used for the reference. The V_REF pin
should always be bypassed to ground with a 0.1 µF capacitor
close to the reference input pin. Lower reference voltages will
decrease the signal-to-noise ratio (SNR) of the ADC11C170.
Increasing the reference voltage (and the input signal swing)
beyond 1.1V may degrade THD for a full-scale input, espe-
cially at higher input frequencies.
It is important that all grounds associated with the reference
voltage and the analog input signal make connection to the
ground plane at a single, quiet point to minimize the effects of
noise currents in the ground path.
The Reference Bypass Pins (V_RP, V_RM, and V_RN) are made
available for bypass purposes. All these pins should each be
bypassed to ground with a 0.1 µF capacitor. A 0.1 µF and a
10 µF capacitor should be placed between the V_RP and V_RN
pins, as shown in Figure 4. This configuration is necessary to
avoid reference oscillation, which could result in reduced SF-
DR and/or SNR. V_RM may be loaded to 1mA for use as a
temperature stable 1.5V reference. The remaining pins
should not be loaded.
Smaller capacitor values than those specified will allow faster
recovery from the power down and sleep modes, but may re-
sult in degraded noise performance. Loading any of these
pins, other than V_RM, may result in performance degradation.
The nominal voltages for the reference bypass pins are as
follows:
V_RM = 1.5 V
V_RP = V_RM + V_REF / 2
V_RN = V_RM − V_REF / 2
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