LM27241 Datasheet, PDF (16/27 Pages) National Semiconductor (TI) – Synchronous Buck Regulator Controller for Mobile Systems

Application Information
CURRENT LIMIT RESISTOR
The timing scheme implemented in the LM27241 makes it
possible for the IC to continue monitoring an over current
condition and to respond appropriately every cycle. This is
explained as follows.
Consider the LM27241 working under normal conditions, just
before an overload occurs. After the end of a given ON-pulse
(say ‘ton1’), the LM27241 starts sampling the current in the
low-side FET. This is the OFF-duration called ‘toff1’ in this
analysis. Therefore, if an over-current condition is detected
during this OFF-duration ‘toff1’, the controller will decide to
omit the next ON-pulse (which would have occurred during
the duration ‘ton2’). This is done by setting an internal ‘over-
current latch’ which will keep HDRV low. The LDRV will now
not only stay high during the present OFF-duration (‘toff1’)
but during the duration of the next (omitted) ON-pulse
(‘ton2’), and then as expected also during the succeeding
OFF-duration (‘toff2’). But the ‘over-current latch’ is reset at
the very start of the next OFF-duration ‘toff2’. Therefore if the
over-current condition persists, it can be recognized during
‘toff2’ and a decision to skip the next ON-pulse (duration
‘ton3’) can be taken. Finally, several ON-pulses may get
skipped until the current in the low-side FET falls below the
current limit threshold.
At the point where current limiting occurs (peak inductor
current becomes equal to current limit) the resistor for setting
the current limit can be calculated. The (peak) current limit
value depends on two factors:
1) The peak current in the inductor with the converter deliv-
ering maximum rated load. This should be calculated at
VIN_MAX
2) The ‘overload margin’ (above maximum load) that needs
to be maintained. This will depend on the step loads likely to
be seen in the application and the response expected. The
peak inductor current under normal operation (maximum
load) depends on the load and the inductance. It is given by:
where I_RIPPLE was determined in the output filter section.
Example: Let I_RIPPLE be 2A. The peak current under normal
operation is
Usually it is necessary to set the current limit about 20%
higher than the peak inductor current. This overload margin
helps handle sudden load changes. A 20% margin will re-
quire a current limit of 11A x 1.2 = 13.2A.
A standard value of 1.37kΩ may be chosen.
A larger overload margin greater than 20% (say 40%) would
help in obtaining good dynamic response. This is necessary
if the load steps from an extremely low value (say zero) up to
maximum load current. A larger current limit will, however,
generate stresses in the FETs during abnormal load condi-
tion (such as a shorted output).
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FIGURE 12. Understanding Current Sensing
For this analysis, the nominal value of current sourced ILIM,
(see Electrical Characteristics table) and the R_{DS_ON} of the
low-side FET at 100˚C should be used. This will ensure
adequate headroom without the need for excessively large
components. From the MOSFET data sheet typical R_{DS_ON}
at 25˚C is given to be 3.7mΩ. This value is not to be used in
the current limit calculation. The maximum FET R_{DS_ON} at
room temperature is 4.8mΩ. During normal circuit operation,
the FET temperature will rise to a temperature greater than
25˚C. Therefore R_{DS_ON} at 100˚C is obtained. From the
datasheet, at 100˚C the R_{DS_ON} goes up typically 1.3 times
its 25˚C value. Therefore, the R_{DS_ON} to be used in the
actual current limit calculation is:
R_{DS_ON} = 1.3 x 4.8 mΩ = 6.42 mΩ
Using I_ILIM = 62µA and a value of 6.42mΩ for maximum
R_{DS_ON} will provide the lowest possible value of current limit
considering tolerances and temperature (for a given R_LIM
resistor). In order to allow for output load transients, it is a
good design practice to add margin to this calculation.
A standard value of 1.58kΩ may be chosen.
Summarizing, for a 1.2V/10A rated output, using a 1.9µH
inductor and any low side equivalent FET (same R_{DS_ON} as
IRF7832).
• For 20% overload margin, select current limit resistor to
be 1.37kΩ
• For 40% overload margin, select current limit resistor to
be 1.58kΩ
INDUCTOR AND OUTPUT CAPACITOR
The designer is again referred to AN-1197 for the equations
required here. The design table in the referenced Application
Note uses V_D as the drop across the diode in an asynchro-
nous configuration. Also, V_SW is the drop across the switch
(high-side FET). In the case of the LM27241 a reasonable
approximation is to set V_D = V_SW = 0 in the design table
available in AN-1197. Then the table can be used easily for
selection of the inductor and output capacitor. A step by step
example is also provided for a general buck regulator in the
Application Note AN-1207 at http://power.national.com.
www.national.com
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