DP83821 Datasheet, PDF (16/86 Pages) National Semiconductor (TI) – 10/100/1000 Mb/s PCI Ethernet Network Interface Controller

3.0 Functional Description (Continued)
3.7.1 VLAN Tag Handling
The Rx MAC can detect packets containing a 4-byte VLAN
tag, and remove the VLAN tag from the received packet. If
RX VLAN Tag removal is enabled, then the 4 bytes
following the source and destination addresses will be
stripped out. The VLAN status can be returned in the
Receive Descriptor Extended Status field.
3.7.2 Carrier Extension and Packet Bursting
The Receive MAC supports reception of packets with
Carrier Extension and packets transmitted using Frame
Bursting for 1000 Mb/s half-duplex operation. The first
frame in a burst must be at least one slotTime in length,
otherwise it will be considered to be a collision fragment.
3.7.3 IP Checksum Verification
The Rx MAC supports IP checksum verification. It can
validate IP checksums as well as TCP and UDP
checksums. Packets can be discarded based on detecting
checksum errors.
3.8 Physical Layer Interface
The DP83821 implements a physical layer interface that
can support all of the following:
— Media Independent Interface (MII)
— Gigabit Media Independent Interface (GMII)
— Ten-Bit Interface (TBI)
In addition, the DP83821 implements a Management
interface as defined for MII and GMII.
3.8.1 Media Independent Interface (MII)
The DP83821 supports 10 Mb/s and 100 Mb/s physical
layer devices through the Media Independent Interface
(MII) as defined in IEEE 802.3 (clause 22). The MII
consists of a transmit data interface (TXEN, TXER,
TXD[3:0], and TXCLK), a receive data interface (RXDV,
RXER, RXD[3:0], and RXCLK), 2 status signals (CRS and
COL) and a management interface (MDC and MDIO). In
this mode of operation, both Transmit and Receive clocks
are supplied by the Phy.
3.8.2 Gigabit Media Independent Interface (GMII)
The DP83821 can support 1000 Mb/s physical layer
devices through the Gigabit Media Independent Interface
(GMII) as defined in IEEE 802.3 (clause 35). The GMII is
extended from the MII to use 8-bit data interfaces and to
operate at higher frequency. The GMII consists of a
transmit data interface (TXEN, TXER, TXD[7:0], and
GTXCLK), a receive data interface (RXDV, RXER,
RXD[7:0], and RXCLK), 2 status signals (CRS and COL)
and a management interface (MDC and MDIO). Many of
the signals are shared with the MII interface. One
significant difference is the Transmit clock (GTXCLK) is
supplied by the DP83821 instead of the Phy. The
management interface (described later) is the same in both
MII and GMII modes
3.8.3 Ten-Bit Interface (TBI)
The TBI provides a port for transmit and receive data for
interfacing to devices that support the 1000Base-X portion
of the 802.3 specification. This includes 1000Base-FX fiber
devices. The port consists of data paths that are 10-bits
wide in each direction as well as control signals. This
interface shares pins with the MII and GMII interfaces.
3.8.4 MII/GMII Management Interface
The MII/GMII management interface utilizes a
communication protocol similar to a serial EEPROM.
Signaling occurs on two signals: clock (MDC) and data
(MDIO). This protocol provides capability for addressing up
to 32 individual Physical Media Dependent (PMD) devices
which share the same serial interface, and for addressing
up to 32 16-bit read/write registers within each PMD. The
MII management protocol utilizes following frame format:
start bits (SB), opcode (OP), PMD address (PA), register
address (RA), line turnaround (LT) and data (See Figure 3-
9).
Figure 3-9 MII Management Frame Format
SB OP PA
2b 2b 5b
RA LT
5b 2b
Data
16b
Note: b = bits
— Start bits are defined as <01>.
— Opcode bits are defined as <01> for a Write access and
<10> for a Read access.
— PMD address is the device address.
— Register address is address of the register within that
device.
— Line turnaround bits will be <10> for Write accesses and
will be <xx> for Read accesses. This allows time for the
MII lines to “turn around”.
— Data is the 16 bits of data that will be written to or read
from the PMD device.
A reset frame is also provided and defined as 32
consecutive 1s (FFFF FFFFh). After power up, all MII PMD
devices must wait for a reset frame to be received prior to
participating in MII management communication.
Additionally, a reset frame may be issued at any time to
allow all connected PMDs to re-synchronize to the data
traffic.
The MII/EEPROM Access Register (MEAR) is used to
provide access to the serial MII.
Refer to Section 4.2.3 for complete details of the MEAR.
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