DAC081C081_08 Datasheet, PDF (16/24 Pages) National Semiconductor (TI) – 8-Bit Micro Power Digital-to-Analog Converter with an I2C-Compatible Interface

1.4.3 High-Speed (Hs) Mode
For Hs-mode, the sequence of events to begin communica-
tion differ slightly from Standard-Fast mode. Figure 5 de-
scribes this in further detail. Initially, the bus begins running
in Standard-Fast mode. The master generates a Start condi-
tion and sends the 8-bit Hs master code (00001XXX) to the
DAC081C081. Next, the DAC081C081 responds with a
NACK. Once the SCL line has been pulled to a high level, the
master switches to Hs-mode by increasing the bus speed and
generating a Repeated Start condition (driving SDA low while
SCL is pulled high). At this point, the master sends the slave
address to the DAC081C081, and communication continues
as shown above in the "Basic Operation" Diagram (see Figure
4).
When the master generates a Repeated Start condition while
in Hs-mode, the bus stays in Hs-mode awaiting the slave ad-
dress from the master. The bus continues to run in Hs-mode
until a Stop condition is generated by the master. When the
master generates a Stop condition on the bus, the bus must
be started in Standard-Fast mode again before increasing the
bus speed and switching to Hs-mode.
FIGURE 5. Beginning Hs-Mode Communication
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1.4.4 I²C Slave (Hardware) Address
The DAC has a seven-bit I²C slave address. For the MSOP-8
version of the DAC, this address is configured by the ADR0
and ADR1 address selection inputs. For the DAC081C081,
the address is configured by the ADR0 address selection in-
put. ADR0 and ADR1 can be grounded, left floating, or tied to
V_A. If desired, the address selection inputs can be set to V_A/
2 rather than left floating. The state of these inputs sets the
address the DAC responds to on the I²C bus (see Table 1).
In addition to the selectable slave address, there is also a
broadcast address (1001000) for all DAC081C081's and
DAC081C085's on the 2-wire bus. When the bus is addressed
by the broadcast address, all the DAC081C081's and
DAC081C085's will respond and update synchronously. Fig-
ure 6 and Figure 7 describe how the master device should
address the DAC via the I²C-Compatible interface.
Keep in mind that the address selection inputs (ADR0 and
ADR1) are only sampled until the DAC is correctly addressed
with a non-broadcast address. At this point, the ADR0 and
ADR1 inputs TRI-STATE and the slave address is "locked".
Changes to ADR0 and ADR1 will not update the selected
slave address until the device is power-cycled.
TABLE 1. Slave Addresses
Slave Address
[A6 - A0]
0001100
0001101
0001110
0001000
0001001
0001010
1001100
1001101
1001110
1001000
DAC081C085 (MSOP-8)
DAC081C081
(TSOT & LLP) *
ADR1
ADR0
ADR0
Floating
Floating
Floating
Floating
GND
GND
Floating
GND
V_A
Floating
V_A
---------------
GND
GND
---------------
GND
V_A
---------------
V_A
Floating
---------------
V_A
GND
---------------
V_A
V_A
---------------
--------------- Broadcast Address ---------------
* Pin-compatible alternatives to the DAC081C081 options are available with additional address options.
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