COP87L88EK Datasheet, PDF(16/41 Page) National Semiconductor (TI) – 8-Bit CMOS OTP Microcontrollers with 8k or 32k Memory, Comparator, and Single-slope A/D Capability

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COP87L88EK Datasheet, PDF (16/41 Pages) National Semiconductor (TI) – 8-Bit CMOS OTP Microcontrollers with 8k or 32k Memory, Comparator, and Single-slope A/D Capability

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Timers (Continued)

The timer mode control bits (TxC3, TxC2 and TxC1) are detailed below:

Mode

TxC3

TxC2

TxC1

Description

PWM: TxA Toggle

PWM: No TxA

Toggle

External Event

Counter

External Event

Counter

Captures:

TxA Pos. Edge

TxB Pos. Edge

Captures:

TxA Pos. Edge

TxB Neg. Edge

Captures:

TxA Neg. Edge

TxB Neg. Edge

Captures:

TxA Neg. Edge

TxB Neg. Edge

Interrupt A

Source

Autoreload RA

Timer

Underflow

Timer

Underflow

Pos. TxA Edge

or Timer

Underflow

Pos. TxA

Edge or Timer

Underflow

Neg. TxA

Edge or Timer

Underflow

Neg. TxA

Edge or Timer

Underflow

Interrupt B

Source

Autoreload RB

Pos. TxB Edge

Neg. TxB

Edge

Neg. TxB

Edge

Neg. TxB

Edge

Timer

Counts On

Pos. TxA

Edge

Pos. TxA

Edge

Power Save Modes

The device offers the user two power save modes of opera-

tion: HALT and IDLE. In the HALT mode, all microcontroller

activities are stopped. In the IDLE mode, the on-board oscil-

lator circuitry the WATCHDOG logic, the Clock Monitor and

timer T0 are active but all other microcontroller activities are

stopped. In either mode, all on-board RAM, registers, I/O

states, and timers (with the exception of T0) are unaltered.

HALT MODE

The device can be placed in the HALT mode by writing a â1â

to the HALT flag (G7 data bit). All microcontroller activities,

including the clock and timers, are stopped. The WATCH-

DOG logic is disabled during the HALT mode. However, the

clock monitor circuitry if enabled remains active and will

cause the WATCHDOG output pin (WDOUT) to go low. If the

HALT mode is used and the user does not want to activate

the WDOUT pin, the Clock Monitor should be disabled after

the device comes out of reset (resetting the Clock Monitor

control bit with the first write to the WDSVR register). In the

HALT mode, the power requirements of the device are mini-

mal and the applied voltage (VCC) may be decreased to Vr

(Vr = 2.0V) without altering the state of the machine.

The device supports three different ways of exiting the HALT

mode. The first method of exiting the HALT mode is with the

Multi-Input Wakeup feature on the L port. The second

method is with a low to high transition on the CKO (G7) pin.

This method precludes the use of the crystal clock configura-

tion (since CKO becomes a dedicated output), and so may

be used with an RC clock configuration. The third method of

exiting the HALT mode is by pulling the RESET pin low.

Since a crystal or ceramic resonator may be selected as the

oscillator, the Wakeup signal is not allowed to start the chip

running immediately since crystal oscillators and ceramic

resonators have a delayed start up time to reach full ampli-

tude and frequency stability. The IDLE timer is used to gen-

erate a fixed delay to ensure that the oscillator has indeed

stabilized before allowing instruction execution. In this case,

upon detecting a valid Wakeup signal, only the oscillator cir-

cuitry is enabled. The IDLE timer is loaded with a value of

256 and is clocked with the tc instruction cycle clock. The tc

clock is derived by dividing the oscillator clock down by a fac-

tor of 10. The Schmitt trigger following the CKI inverter on

the chip ensures that the IDLE timer is clocked only when the

oscillator has a sufficiently large amplitude to meet the

Schmitt trigger specifications. This Schmitt trigger is not part

of the oscillator closed loop. The startup timeout from the

IDLE timer enables the clock signals to be routed to the rest

of the chip.

If an RC clock option is being used, the fixed delay is intro-

duced optionally. A control bit, CLKDLY, mapped as configu-

ration bit G7, controls whether the delay is to be introduced

or not. The delay is included if CLKDLY is set, and excluded

if CLKDLY is reset. The CLKDLY bit is cleared on reset.

The device has two mask options associated with the HALT

mode. The first mask option enables the HALT mode feature,

while the second mask option disables the HALT mode. With

the HALT mode enable mask option, the device will enter

and exit the HALT mode as described above. With the HALT

disable mask option, the device cannot be placed in the

HALT mode (writing a â1â to the HALT flag will have no effect,

the HALT flag will remain â0â).

The WATCHDOG detector circuit is inhibited during the

HALT mode. However, the clock monitor circuit if enabled re-

mains active during HALT mode in order to ensure a clock

monitor error if the device inadvertently enters the HALT

mode as a result of a runaway program or power glitch.

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