LMX2531 Datasheet, PDF (15/36 Pages) National Semiconductor (TI) – High Performance Frequency Synthesizer System with Integrated VCO

Symbol
V_IH
V_IL
I_IH
I_IL
V_OH
V_OL
t_CS
t_CH
t_CWH
t_CWL
t_ES
t_CES
t_EWH
Parameter
Conditions
Digital Interface (DATA, CLK, LE, CE, Ftest/LD, FLout)
High-Level Input Voltage
Low-Level Input Voltage
High-Level Input Current
Low-Level Input Current
High-Level Output Voltage
Low-Level Output Voltage
V_IH = 1.75
V_IL = 0 V
I_OH = 500 µA
I_OL = -500 µA
MICROWIRE Timing
Data to Clock Set Up Time
See Data Input Timing
Data to Clock Hold Time
See Data Input Timing
Clock Pulse Width High
See Data Input Timing
Clock Pulse Width Low
See Data Input Timing
Clock to Enable Set Up Time
See Data Input Timing
Enable to Clock Set Up Time
See Data Input Timing
Enable Pulse Width High
See Data Input Timing
Min Typ Max
1.6
2.75
0.4
-3.0
3.0
-3.0
3.0
2.0 2.65
0.0 0.4
25
20
25
25
25
25
25
Units
V
V
µA
µA
V
V
ns
ns
ns
ns
ns
ns
ns
Note 2: There are program bits that need to be set based on the OSCin frequency. Refer to the following sections: 2.7.8 XTLSEL[2:0] -- Crystal Select, 2.8.1
XTLDIV[1:0] -- Division Ratio for the Crystal Frequency, 2.8.2 XTLMAN[11:0] -- Manual Crystal Mode, 2.9.1 XTLMAN2 -- MANUAL CRYSTAL MODE SECOND
ADJUSTMENT, and2.9.2 LOCKMODE -- FREQUENCY CALIBRATION MODE. Not all bit settings can be used for all frequency choices of OSCin. For instance,
automatic modes described in 2.7.8 XTLSEL[2:0] -- Crystal Select do not work below 8 MHz.
Note 3: One of the specifications for modeling PLL in-band phase noise is the PLL 1/f noise normalized to 1 GHz carrier frequency and 10 kHz offset, L_{PLL_flicker}
(10 kHz). From this normalized index of PLL 1/f noise, the PLL 1/f noise can be calculated for any carrier and offset frequency as:
LN_{PLL_flicker}(f) = L_{PLL_flicker}(10 kHz) - 10·log(10 kHz / f) + 20·log( Fout / 1 GHz ). Flicker noise can dominate at low offsets from the carrier and has a 10 dB/decade
slope and improves with higher charge pump currents and at higher offset frequencies . To accurately measure L_{PLL_flicker}(10 kHz) it is important to use a high
phase detector frequency and a clean reference to make it such that this measurement is on the 10 dB/decade slope close to the carrier. L_{PLL_flicker}(f) can be
masked by the reference oscillator performance if a low power or noisy source is used. The total PLL in-band phase noise performance is the sum of L_{PLL_flicker}
(f) and L_{PLL_flat}. In other words,L_PLL(f) = 10·log(10(^LNPLL_flat ^{/ 10 )} + 10(^LNPLL_flicker ^{(f) / 10 )}
Note 4: A specification used for modeling PLL in-band phase noise floor is the Normalized PLL noise floor, LN_{PLL_flat}, and is defined as:
LN_{PLL_flat} = L(f) – 20·log(N) – 10·log(f_PD). L_{PLL_flat} is the single side band phase noise in a 1 Hz Bandwidth and f_PD is the phase detector frequency of the synthesizer.
L_{PLL_flat} contributes to the total noise, L(f). To measure L_{PLL_flat} the offset frequency must be chosen sufficiently smaller then the loop bandwidth of the PLL, and
yet large enough to avoid a substantial noise contribution from the reference and PLL flicker noise. L_{PLL_flat} can be masked by the reference oscillator performance
if a low power or noisy source is used. The total PLL in-band phase noise performance is the sum of L_{PLL_flicker}(f) and L_{PLL_flat}. In other
words,L_PLL(f) = 10·log(10(^LNPLL_flat ^{/ 10 )} + 10(^LNPLL_flicker ^{(f) / 10 )}
Note 5: Maximum Allowable Temperature Drift for Continuous Lock is how far the temperature can drift in either direction from the value it was at the time that
the R0 register was last programmed, and still have the part stay in lock. The action of programming the R0 register, even to the same value, activates a frequency
calibration routine. This implies that the part will work over the entire frequency range, but if the temperature drifts more than the maximum allowable drift for
continuous lock, then it will be necessary to reload the R0 register to ensure that it stays in lock. Regardless of what temperature the part was initially programmed
at, the temperature can never drift outside the frequency range of -40°C ≤T_A≤ 85°C without violating specifications.
Note 6: The VCO phase noise is measured assuming that the loop bandwidth is sufficiently narrow that the VCO noise dominates. The maximum limits apply
only at center frequency and over temperature, assuming that the part is reloaded at each test frequency. Over frequency, the phase noise can vary 1 to 2 dB,
with the worst case performance typically occurring at the highest frequency. Over temperature, the phase noise typically varies 1 to 2 dB, assuming the part is
reloaded.
15
www.national.com