DS32EL0124_0807 Datasheet, PDF (15/26 Pages) National Semiconductor (TI) – 125 MHz . 312.5 MHz Deserializer with DDR LVDS Parallel Interface

DEVICE CONFIGURATION
There are four ways to configure the DS32EL0124 and
DS32ELX0124 devices, these combinations are shown in
Table 1. Refer to Figure 7 to see how the combinations of the
RS and DC_B pins change the link startup behavior of the
deserializers. When connecting to a serializer other than the
DS32EL0421 or DS32ELX0421, Remote Sense should be
disabled. The descrambler and NRZI decodeer shown in Ta-
ble 1 can be enabled or disabled through register program-
ming.
When Remote Sense is enabled, with RS pin tied low, the
deserializer must be connected directly to a DS32EL0421/
DS32ELX0421 serializer without any active components be-
tween them. The Remote Sense module features both an
upstream and downstream communication method for the
serializer to detect a deserializer and vice versa. This feature
is used to pass link status information between the 2 devices.
If DC-Balance is enabled, the maximum number of parallel
LVDS lanes is four. The fifth lane becomes a Data Valid signal
(TXIN4±). Every time a DS32EL0421/DS32ELX0421 serial-
izer establishes a link to a DS32EL0124/DS32ELX0124 de-
serializer with DC-Balance enabled, the Data Valid input to
the serializer must be held high for 20 LVDS clock periods. If
the Data Valid input to the serializer is logic high, then SYNC
TABLE 1. Device Configuration Table
characters are transmitted. If the deserializer receives a
SYNC character, then the LVDS data outputs will all be logic
low and the Data Valid outputs will be logic high. If the dese-
rializer detects a DC-Balance code error, the output data pins
will be set to logic high with the Data Valid output also set to
logic high.
In the case where DC-Balance is enabled and Remote Sense
is disabled, with RS set to high and DC_B set to low, an ex-
ternal device must toggle the Data Valid input to the serializer
periodically to ensure constant lock. With these pin settings
the devices can interface with other active component in the
high speed signal path, such as fiber modules.
When both Remote Sense and DC-Balance are disabled,
RS and DC_B pins set to high, the LVDS lane alignment is
not maintained. In this configuration, data formatting is han-
dled by an FPGA or external source. In this mode the dese-
rializer locks to incoming random data. To achieve lock during
the clock acquisition phase, the incoming data should have a
“101” or “010” transition density of approximately 25%.
Scrambling and NRZI encoding can be implemented to help
improve the transition density of the data. This pin setting also
allows for the devices to interface with other active compo-
nents in the high speed signal path.
Remote Sense Pin (RS)
0
0
1
1
DC-Balance Pin(DC_B)
0
1
0
1
Configuration
Remote Sense enabled
DC-Balance enabled
Data Alignment
De-Scrambler and NRZI decoder disabled by default
Remote Sense enabled
DC-Balance disabled
Data Alignment
De-Scrambler and NRZI decoder enabled by default
Remote Sense disabled
DC-Balance enabled
Data Alignment
De-Scrambler and NRZI decoder enabled by default
Remote Sense disabled
DC-Balance disabled
No Data Alignment
De-Scrambler and NRZI decoder disabled by default
15
www.national.com